Semiconductor Value Chain Glossary

Software tools used by chip designers to create, simulate, verify, and optimize semiconductor designs. Required to design any modern chip.

A reusable block of logic — e.g. a CPU core, USB controller, or memory interface — licensed to chip designers rather than designed from scratch. ARM CPU cores are the most widely licensed IP in history.

A chip company that designs semiconductors but outsources manufacturing to a foundry. No factory ("fab") ownership. Examples: NVIDIA, AMD, Apple (for its own chips), Qualcomm, Broadcom.

A company that both designs and manufactures its own chips. Examples: Intel, Samsung, Micron. Capital-intensive but maintains end-to-end control.

A semiconductor manufacturer that makes chips for other companies (fabless firms). TSMC is the dominant pure-play foundry, manufacturing nearly 90% of advanced chips globally.

A thin disc of silicon (typically 300mm diameter) on which hundreds of chips are simultaneously manufactured. The basic unit of foundry production. Chip yield = percentage of working chips per wafer.

A marketing label (loosely tied to transistor dimensions) indicating the generation of manufacturing process. Smaller nodes → more transistors per mm², better performance/watt. Labels are not literal measurements.

The process of printing circuit patterns onto silicon wafers using light. The central step in chip manufacturing. EUV (Extreme Ultraviolet) lithography enables the smallest, most advanced patterns.

Lithography technology using 13.5nm wavelength light to pattern sub-10nm features on chips. Requires plasma-generated light, ultra-precise optics, and a near-perfect vacuum. Only ASML manufactures EUV machines.

Technologies that combine multiple chips (or dies) into one package — connecting them at high bandwidth with short distances. Increasingly determines AI chip performance. Examples: NVIDIA H100/H200 use CoWoS packaging with HBM memory.

Stacked DRAM memory architecture that sits adjacent to (or on top of) a GPU/accelerator die. Provides much higher memory bandwidth than conventional DRAM. Essential for LLM inference and training. Made primarily by SK Hynix, Samsung, Micron.

NVIDIA's parallel computing platform and programming model. The software ecosystem that makes NVIDIA GPUs the default for AI/ML workloads. Launched 2006. Nearly every major AI framework (PyTorch, TensorFlow) is optimized for CUDA.

An open-source instruction set architecture (ISA) — a free alternative to ARM's proprietary ISA. Growing adoption in edge chips, custom accelerators, and China (where ARM access is restricted).

Paradigm proposed by Huawei (He Tingbo, ISCAS 2026). Replaces transistor geometric scaling (Moore's Law) with "temporal scaling" — minimizing the RC time constant (τ) by shortening signal path lengths via 3D chip layout. Implemented through LogicFolding. First commercial chip: Kirin 2026 (autumn 2026).

Huawei's intra-die 3D chip design method. Folds 2D circuit routing paths into vertical layers within a single die, shortening wire lengths and reducing RC time constants. Distinct from chiplet integration (which bonds separate finished dies). Requires new EDA tooling — Peking University built the first tool in May 2026.

In electronics: the time it takes a signal to charge/discharge through a wire. τ = Resistance × Capacitance. Lower τ = faster signal propagation. Wire length is the primary driver — shorter wire = lower R and C = lower τ. The physical basis for Tao's Law.

The traditional path of Moore's Law: shrink the physical size of transistors to pack more per mm², improving performance and efficiency. Now decelerating as transistors approach atomic scale (~3nm = ~10 atoms across). EUV lithography is required to continue below ~7nm economically.

Technique to achieve smaller feature sizes using older Deep Ultraviolet (DUV) lithography machines by exposing the same wafer layer multiple times with shifted masks. SMIC uses this to produce "7nm" chips without EUV. Results in lower yield (~20–40% vs TSMC's 90%+), longer production time, and higher cost per chip.