Where every chip comes from — and where the money actually gets made
Every AI chip that trains a language model, every GPU powering a data center, every phone processor — all of them move through the same chain of companies before they exist as physical silicon. Understanding who does what in that chain is the single most important map for both investment and technical judgment in this space.
Most financial analysis skips the chain and jumps straight to stock picks. Most technical coverage skips the economics. This lesson gives you both at once.
A chip travels through five distinct layers before it reaches a data center or a device:
There is also a sixth, often-overlooked layer: advanced packaging (CoWoS, HBM stacking, chiplets). This is where multiple chips are combined into one package — increasingly where AI chip performance is determined. More on this in a future lesson.
Before a single transistor is manufactured, a chip must be designed — and chip design is unfathomably complex. A modern chip like NVIDIA's Blackwell contains over 200 billion transistors, each connected by miles of microscopic wiring. No human can place these by hand.
EDA tools are the software that semiconductor engineers use to design, simulate, and verify chips. Without them, no chip gets built. Synopsys and Cadence together control roughly 70–80% of the EDA market — a duopoly that has persisted for decades.
Chip designers don't build everything from scratch. They license proven circuit blocks — called IP cores (intellectual property cores) — for things like CPUs, GPUs sub-units, USB controllers, and memory interfaces.
ARM dominates CPU IP. Every iPhone, Android phone, and most AI accelerators use ARM CPU cores. ARM does not manufacture chips — it sells the right to use its architectural blueprints. This is a royalty + licensing business: low capex, very high margins, compounding.
The most glamorous layer. Fabless companies design chips but do not own factories. They hand their designs to a foundry (Layer 4) for manufacturing. This model was pioneered in the 1980s by Morris Chang's insight that chip design and manufacturing could be separated.
The fabless model freed designers from the crushing capital cost of building fabs (a modern fab costs $15–30B+). It concentrated manufacturing expertise at a small number of world-class foundries. Today, the most valuable semiconductor companies — NVIDIA, AMD, Qualcomm, Apple (for its own chips), Broadcom — are all fabless.
Some companies are IDMs (Integrated Device Manufacturers) — they design and manufacture their own chips. Intel is the canonical example; Samsung and Micron also qualify. IDMs require massive capital investment but maintain tighter control over manufacturing. Intel's struggles over the past decade partly reflect the burden of maintaining leading-edge fab capability while competing against pure-play foundries.
This is the hardest layer to enter, and the most strategically important. A foundry (or "pure-play foundry") does nothing but manufacture — it takes chip designs from fabless customers and produces wafers.
TSMC (Taiwan Semiconductor Manufacturing Company) manufactures nearly 90% of the world's most advanced chips. This is not an accident of geography — it is the result of 35 years of relentless operational excellence, capital investment, and trust built with customers.
TSMC's advanced fabs sit 110 miles from mainland China. This is not a peripheral risk — it is the central geopolitical risk of the AI era. A blockade or conflict would halt global chip production for advanced AI and consumer devices simultaneously. This single fact drives US policy (CHIPS Act), NVIDIA's supply chain anxiety, and TSMC's reluctant expansion to Arizona and Japan. [Acquired TSMC episode]
To manufacture chips, foundries need specialized machines. Equipment companies build these machines — and some of them hold absolute monopolies on critical tools.
ASML (Netherlands) is the sole manufacturer of EUV (Extreme Ultraviolet) lithography machines — the machines that print the most advanced chip patterns. A single EUV machine costs ~$150–200M, takes a year to install, and requires 400,000 components. No EUV machine, no leading-edge chip. No one else makes EUV machines. Not in the US. Not in Japan. Not in China. Only ASML.
Every layer has a different competitive structure. Here is the snapshot that should drive how you weight opportunity vs. stability when analyzing companies in this space:
| Layer | Structure | Key moat | Gross margins | Key risk |
|---|---|---|---|---|
| EDA Tools | Duopoly | Switching costs, workflow lock-in | ~80–85% | Open-source EDA (nascent) |
| IP Cores (ARM) | Monopoly | Architecture ecosystem, ISA adoption | ~95%+ | RISC-V displacement (long-term) |
| Chip Design | Competitive | Varies: CUDA ecosystem (NVIDIA), silicon-software co-design (Apple) | 50–70% | Customer in-house design; new entrants |
| Foundry | Oligopoly | Process knowledge, yield, customer trust | ~50–55% | Geopolitical disruption; Samsung/Intel catching up |
| EUV Equipment | Monopoly | Physics-driven natural monopoly; irreplicable supply chain | ~50–55% | Export restrictions limiting TAM; next-gen NA-EUV transition |
| Other Equipment | Oligopoly | Process expertise, installed base | 45–55% | Capital spending cycles; CHIPS Act distortions |
Answer from memory. No scrolling up. The friction is the learning.
Recommended: Acquired Podcast — TSMC (Remastered, 2025) (~4 hours). This is the best single narrative on why TSMC's manufacturing moat exists and how the fabless/foundry separation came about. Listen to the first 90 minutes at minimum. It transforms an abstract value chain into a concrete story.
Also recommended: Chip War — Chris Miller (book, ~400 pages). Chapter 1–15 covers how each layer of today's value chain was created historically — which gives you a much stronger mental model of why the moats are where they are.