Huawei's Tao (τ) Law

Context: Why China had to find a different game

From Lesson 1 you know why China can't catch TSMC by playing the same game: no EUV machines, no accumulated process knowledge, no global equipment supply chain. SMIC's best result at 7nm DUV multi-patterning yields 20–40% — wildly uneconomical without state subsidies.

Conventional industry wisdom said China's only options were: (a) wait decades to build its own supply chain, (b) hope export controls loosen, or (c) stay on mature nodes and accept permanent inferiority at the cutting edge. Huawei just proposed a fourth option: redefine what "cutting edge" means.

To understand why Tao's Law is the proposal it is, you first need to understand the law it proposes to replace.

Moore's Law — and why it's dying

In 1965, Gordon Moore (co-founder of Intel) observed that the number of transistors on a chip doubled approximately every two years. For 60 years, the industry treated this as a roadmap and delivered on it — giving us exponentially more computing power at exponentially lower cost.

The mechanism was simple: shrink the transistor. Smaller transistors → more per mm² → more compute per watt → better performance. This is geometric scaling: the metric is transistor size in nanometers, which the industry races to minimize.

The problem: physics. Transistors are now ~3nm — roughly 10–15 atoms across. You cannot shrink silicon indefinitely. Quantum tunneling effects cause electrons to leak where they shouldn't. Fabricating at these scales requires EUV lithography and increasingly exotic materials. Each new node takes more time, costs more money, and delivers smaller performance gains than the last. The industry calls this "slowing geometric scaling" — Moore's Law is decelerating.

The industry's response has already moved away from pure transistor shrinking toward architectural innovation: chiplets, 3D stacking, specialized accelerators. What Huawei is proposing is an explicit, named version of this shift.

What τ (tau) actually is

τ is not invented by Huawei. It is a fundamental constant in electronics: the RC time constant.

The critical insight: τ is proportional to wire length. Longer wire = higher R and C = slower signals. Moore's Law made transistors smaller, which helped some. But as chips grew more complex, the wires connecting those transistors got longer — and those wires increasingly bottleneck performance.

Huawei's argument: stop obsessing over transistor size. Start obsessing over wire length. Minimize τ directly. This is the shift from "geometric scaling" to "temporal scaling."

LogicFolding — the technical implementation

The mechanism Huawei proposes to reduce τ is called LogicFolding. The idea: take a traditional 2D circuit layout — the flat grid of logic blocks connected by wires — and physically fold it into 3D vertical layers, like folding a long printed circuit board into a compact stack.

The result:

• Signals that used to travel across the chip horizontally now travel a few layers vertically
• Shorter paths → lower R, lower C → lower τ → faster clock speeds and lower power
• More transistors per mm² of footprint (density improvement)
• Peking University reported 30% reduction in total internal wire length in early open-source circuit tests using a new EDA tool built specifically for LogicFolding

How is this different from existing 3D packaging?

This is the crucial technical distinction — and where most coverage gets it wrong.

The key word is intra-die. Existing 3D solutions stack separate chips together. LogicFolding claims to fold the internal routing of a single chip — a finer-grained operation that requires redesigning how place-and-route tools work from the ground up. That's why Peking University had to build a new EDA tool: the existing Synopsys/Cadence tools aren't designed for vertical-first layout.

Huawei's claimed roadmap

The three problems Huawei doesn't advertise

1. Heat — the physics wall that doesn't move

When you stack logic vertically, you double or triple heat density in the same footprint. Bottom layers are trapped beneath top layers — a "thermal blanket" effect. Heat can't escape downward (the substrate blocks it); it must go up through the stack or sideways. This causes thermal throttling (the chip automatically slows down to avoid melting) and long-term reliability degradation. In a flat 2D chip, heat escapes easily upward.

HBM memory already faces this problem in AI GPUs — and those are memory stacks, not logic stacks (logic generates far more heat per mm²). TSMC's SoIC uses active interposers with microfluidic cooling research precisely because of this. LogicFolding's heat solution has not been publicly described.

2. The EDA ecosystem is not ready

Designing a chip for LogicFolding requires tools that can optimize across vertical layers simultaneously — not just partition separate layers independently. This is a new class of place-and-route problem. Peking University built one tool for it. But the full EDA flow (synthesis, timing analysis, power analysis, design rule checking, verification) all need to be 3D-aware. That's years of toolchain work, and China is also restricted from the latest Synopsys and Cadence versions under export controls. [Tom's Hardware]

3. "Equivalent density" ≠ equivalent performance

Huawei claims 1.4nm-equivalent density by 2031. This is a transistor count per mm² figure. But chip performance depends on more than transistor density: clock speed, memory bandwidth, interconnect latency, power envelope, manufacturing yield. A chip with "1.4nm-equivalent density" built on 7nm DUV with LogicFolding may have worse clock speed and higher leakage current than a genuine 1.4nm chip from TSMC. The density headline may be accurate; the performance implication is not guaranteed to follow.

Investment implications — the map changes

The bottom line

Tao's Law is neither the geopolitical chip war breakthrough Chinese state media wants it to be, nor the irrelevant hype Western dismissals suggest. It is a technically serious proposal from an engineering team that has consistently outperformed expectations under extraordinary constraints — backed by real physics, early results, and a first commercial chip due this autumn.

The correct investor posture right now:

1. Track the Kirin 2026 launch (autumn 2026). TechInsights will teardown the chip. Look for independent confirmation of the 238M/mm² density claim and — more importantly — actual performance benchmarks against TSMC 5nm or 3nm parts.
2. Watch Chinese hyperscaler procurement. If Alibaba, Baidu, and ByteDance start deploying Ascend AI chips at scale (and reducing NVIDIA orders), Tao's Law is working in the only market that matters for China's AI chip supply chain.
3. Don't update TSMC or ASML positions on this announcement alone. The moats in Lesson 1 are intact. Tao's Law is a parallel path, not a disruption of the existing one.
4. Revisit the SMIC thesis. If LogicFolding proves out, existing 7nm DUV capacity becomes strategically more valuable than it looked six months ago.

Primary sources

• SemiconAlpha — "Tau Scaling Law and LogicFolding: Desperation, A Genuine Breakthrough, Or Both?" — The most balanced technical take. Required reading before forming a view.
• Tom's Hardware — "Huawei Claims 1.4nm-Class Chips by 2031" — Solid technical summary with good skepticism on the claims.
• Futurum Group — "Does Tao's Law Challenge Intel and TSMC's Logic Leadership?" — Investment-oriented analysis.

What comes next

• Lesson 3: Inside NVIDIA's real moat — why CUDA's 18-year ecosystem lead matters more than GPU transistor counts, and how to evaluate whether AMD or custom silicon (TPU, Trainium) can close the gap
• Lesson 4: The transformer architecture — why the attention mechanism determines which hardware characteristics win, from first principles