Reference · Chips & LLMs

The Decode Protocol

Run every chip/AI announcement through these five steps. Keep next to THESIS.md. From Lesson 26.

1STRIP — claim vs. marketing

What is the literal number, with the spin removed?

2MECHANISM — real or framed?

What physical lever produced the gain, and what was traded away?

Lever: HBM capacity/bandwidth · lower precision · bigger die · interconnect · packaging/process.
Omission: power · yield · generality · a missing piece of the stack (e.g. software, qualification).
Default verdict is usually "real but framed."

3FALSIFIER — the step analysts skip

Which name(s), and which THESIS.md falsifier moved — toward or away?

triggeredthesis breaks — act approachinglive, not met — watch holdsno movement recedesbull reinforced

4SIZING — does the book change?

Conviction, or independence?

Rule: size = conviction × falsifier-independence.
Most news moves conviction a notch. Raise it freely.
Almost nothing moves independence — reinforcing the shared AI-capex factor does not diversify. Treat independence shifts as rare and important.

5NEXT SIGNAL — keep the thesis alive

What single observable resolves this next quarter?

Name one concrete, checkable event; add it to the quarterly watch-list in THESIS.md.

Falsifier quick-reference (the watch-list)

Name	Triggered if…
TSMC	Samsung/Intel wins a flagship leading-edge customer at volume with competitive yield; or CoWoS stops being the binding constraint.
NVIDIA	A qualified, rack-scale NVSwitch-equivalent fabric adopted at hyperscaler volume; or ROCm reaches CUDA parity (<5–10%); or ASIC mix takes material share. Watch DC gross-margin trend.
Broadcom	Major ASIC customers in-source design; or GPU stays cheaper/more flexible for the marginal workload; or Ethernet scale-out share stalls.
SK Hynix	Samsung gets full HBM4 NVIDIA qual at volume; or HBM supply outruns demand (ASPs roll); or SSM/hybrid adoption cuts KV-cache HBM.
ASML	A credible second EUV source reaches volume; or High-NA adoption is materially deferred; or a sustained down-cycle in net EUV bookings.
AMD	Confirmed: ships qualified rack-scale Helios/UALink at volume AND ROCm near-parity. Broken: fails to gain inference share despite competitive specs.
Cadence / Synopsys	A third/open-source flow wins production tape-outs at an advanced node; or a customer cohort in-sources tooling; or design starts structurally decline.
Power leg	(The orthogonal hedge.) Grid/PPA/transformer constraints prevent ordered GPUs from being energized — shipments decouple downward from bookings.

The falsifier column is the rebalancing trigger. Check it every earnings season: did anything move toward triggered?