# THESIS.md — Living Per-Name Investment Theses **The durable-judgment artifact.** For each name: bull case, bear case, the *key technical assumption* the bull case rests on, and the *falsifier* — the specific, observable signal that would force you to change your mind. Update this **every lesson**. The falsifier is the most important field: a thesis you can't falsify is a belief, not an analysis. Created 2026-06-20 at Checkpoint 1 (after L1–L15). Grounded names (TSMC, NVDA, AVGO, SK Hynix) have lesson coverage; ASML, AMD, Cadence/Synopsys are stubbed from cross-references and will be deepened at L16 (AMD), L17 (ASML), L18 (EDA). Conviction scale: ★ low / ★★ medium / ★★★ high (confidence in the *durability* of the moat, not a price call). --- ## TSMC — ★★★ (grounded: L4, L5) - **Bull:** Structural monopoly on leading-edge logic *and* advanced packaging (CoWoS). Three compounding moats — yield learning curve, customer-trust ecosystem (pure-play, never competes with customers), and capital + first access to ASML tools. CoWoS is now the literal gate on Blackwell shipments, so TSMC captures value whether NVIDIA *or* AMD wins the GPU socket. - **Bear:** Geopolitical concentration risk (Taiwan). Customer concentration (NVIDIA + Apple). Arizona/Japan fabs dilute the cost advantage. A demand air-pocket if AI capex over-builds. - **Key technical assumption:** Leading-edge yield is an accumulated learning curve that capital alone cannot shortcut → no fast-follower can close the gap. - **Falsifier:** Samsung or Intel Foundry wins a *flagship* leading-edge customer (e.g. an NVIDIA or Apple flagship SoC) at volume with competitive yield; OR CoWoS capacity stops being the binding constraint (others reach packaging parity). ## NVIDIA (NVDA) — ★★★ moat today, ★★ durability (grounded: L6, L13, L15) - **Bull:** Three-layer moat — (1) NVSwitch *rack-scale topology* enabling TP=72 (NVL72), a physics-based gap competitors can't currently match; (2) CUDA software ecosystem, 15+ yrs of kernels; (3) full-stack systems integration. Inference demand (recurring) growing faster than training. FP4 + disaggregated serving extend the lead into production inference. - **Bear:** Layer 1 is *engineering, not physics law* — AMD rack-scale InfinityFabric or hyperscaler ASICs can erode it over 2–3 yrs. Layer 2 erodes as hyperscalers fund ROCm/Triton/ XLA. Customer concentration in a few hyperscalers who are also building their own silicon. Margins this high invite attack. Cyclical capex risk. - **Key technical assumption:** TP's per-layer all-reduce *requires* NVLink-class bandwidth, and no one ships a rack-scale equivalent → NVL72 is uniquely capable for large training + long- context inference. - **Falsifier:** AMD (or anyone) ships a *qualified, rack-scale* NVSwitch equivalent adopted by a major hyperscaler; OR ROCm reaches CUDA throughput parity (<5% gap) in production; OR hyperscaler ASIC mix displaces a material share of NVIDIA training/inference volume. - **Demand-side falsifier (added L20, power):** Power becomes the binding cap on *realized* demand — grid-interconnect queues, PPA availability, and transformer/turbine backlogs prevent ordered GPUs from being energized, so shipments decouple downward from bookings. Watch interconnection approvals + hyperscaler PPA volume as a *leading* indicator for NVDA/AVGO realized (vs. nameplate) demand. See [[0022-datacenter-power-energy-lesson20]]. - **LIVE READ (GTC 2026 + Q1 FY27, decoded L26):** **Vera Rubin** claims "up to ~10× lower inference token cost vs Blackwell" (system-level, FP4, first cloud deploys) → extends the lead into *production inference* and pushes AMD's inference-wedge falsifier *the wrong way*. The **~$20B Groq acquisition** = NVDA defending the inference-ASIC turf in-house (a read-through to the AVGO ASIC-TAM falsifier). **Q1 FY27 earnings:** rev $81.6B (+85%), Data Center $75.2B (+92% YoY) → the **capex-air-pocket falsifier recedes** (no demand cliff). The live tripwire on NVDA remains the **data-center gross-margin trend** (erosion toward low-60s = competition biting), which a single blowout print does *not* move. Sources: CNBC (GTC 2026); NVIDIA 8-K (SEC). ## Broadcom (AVGO) — ★★★ (grounded: L10; networking L13; XPU model L28) - **Bull:** The merchant arms dealer for custom AI silicon (XPU/ASIC design services for Google TPU v5p/v6, Meta MTIA v2 — both confirmed). Revenue model: NRE ($300–700M/design win, one-time, nearly pure margin) + per-chip volume ($30–80/chip, recurring for chip lifetime) + networking revenue from Tomahawk/Jericho in the same clusters. Gets paid as hyperscalers diversify *away* from NVIDIA — a structural hedge. Hock Tan guided $60–90B serviceable AI TAM across major XPU customers by FY2027. Sticky: hyperscalers lack AVGO's 10+ generations of custom silicon expertise and would need 5–8 years to replicate (Amazon proved it takes that long). - **Bear:** Revenue is lumpy — NRE recognized over design cycle, then switches to volume; a delayed chip generation or reduced order can crater quarterly AI revenue even if the relationship is intact. Amazon (Annapurna in-house) and Microsoft (Marvell + internal) show the alternative path exists. If Google or Meta accumulates sufficient silicon design headcount (7,000+ engineers like Apple), in-sourcing becomes viable within a decade. The NVIDIA Groq acquisition (~$20B) signals NVIDIA will offer a more complete inference stack, potentially reducing new XPU design wins for inference chips. - **Key technical assumption:** The hyperscaler silicon bet pencils only at extreme volume (100K+ GPU equivalents) AND workload stability (3–4 yr design cycle must not obsolete the chip). Google and Meta currently meet both; the question is whether new entrants (OpenAI, ByteDance, Apple AI servers) will choose the AVGO route or the Amazon route. - **Falsifier (sharpened, L28/L29):** (1) Google or Meta engineering disclosures reveal a staffed-up internal ASIC design org (watch headcount reporting + job postings in semiconductor design roles); OR (2) AVGO misses its FY2027 AI revenue guide by >20% due to customer design-win delays — the lumpiness risk made visible; OR (3) Ethernet share stalls because InfiniBand + SHARP recaptures hyperscaler scale-out — this kills the Tomahawk networking leg (~$6 B of ~$12 B AI revenue). Watch: (a) hyperscaler switch-fabric procurement disclosures, (b) UEC adoption pace relative to SHARP-on-Ethernet timeline, (c) any named hyperscaler switching its custom cluster to InfiniBand. - **Networking leg mechanism (L29):** Tomahawk 5 (51.2 Tbps, 64 × 800G) dominates Ethernet switch silicon in hyperscaler AI clusters. GPU vendor and switch-silicon vendor are separate decisions — even NVIDIA GPU clusters use AVGO Tomahawk for scale-out. Only NVIDIA-resold DGX SuperPODs use InfiniBand (NVDA) end-to-end. Growing tailwind: AMD Helios uses UALink-over-Ethernet, meaning AMD cluster growth also drives Tomahawk revenue. CPO (co-packaged optics) is the next networking revenue leg (~2026–2028); AVGO controls the switch die and holds silicon photonics IP. - **HBM note (L28):** Not all ASIC programs use heavy HBM. Inference ASICs designed for on-chip SRAM decode (Groq LPU model) reduce per-chip HBM content. Watch HBM content per ASIC vs per GPU in hyperscaler procurement data — a divergence would update the SK Hynix cross-read. ## SK Hynix — ★★ (grounded: L12; demand from L13, L15) - **Bull:** HBM share leader (~50%) and first-to-qualify on HBM3e for NVIDIA. HBM content per GPU rising fast (B200 = 8 stacks vs H100's ~5; HBM4 doubles bus width). Demand is gated by yield, so pricing power is real while supply is tight. Direct leverage to every GPU sold, NVIDIA *or* AMD. - **Bear:** Memory is historically the most cyclical, commoditized semi segment. Samsung re-qualification on HBM3e/HBM4 is the key pricing risk (duopoly → oligopoly margin compression). Capacity additions could overshoot if AI capex normalizes. - **Key technical assumption:** HBM stays supply-constrained (yield-gated) and SK Hynix holds its qualification/yield lead → HBM behaves like a premium product, not a commodity. - **Falsifier:** Samsung achieves full HBM3e/HBM4 NVIDIA qualification at volume (restores 3-way price competition); OR HBM supply outruns demand and ASPs roll over; OR a memory architecture shift reduces HBM content per accelerator — **concrete mechanism (L23): broad SSM/hybrid (Mamba/ Jamba) adoption replaces the linearly-growing KV cache with a fixed-size state, cutting HBM needed for long context. Watch frontier hybrid adoption.** See [[0025-moe-ssm-lesson23]]. (Counter-force: MoE raises *total*-param HBM footprint → net depends on the architecture mix.) ## ASML — ★★★ (grounded: L17) - **Bull:** Sole supplier of EUV and High-NA EUV lithography — a true monopoly at the foot of the entire leading-edge value chain. Resolution is set by wavelength (CD = k₁·λ/NA) and ASML is the only firm that productized 13.5 nm light. Gets paid regardless of which foundry or chip vendor wins downstream. ~50%+ gross margin, monopoly pricing, and a large recurring installed-base service/upgrade business that smooths the cycle. High-NA (~$380M/system) = the next ASP super- cycle. Export controls make it the central geopolitical lever. - **Bear:** Extreme customer concentration (TSMC/Samsung/Intel + memory). Bookings are lumpy and tied to the foundry/memory capex cycle — an AI capex air-pocket hits the order book first. China revenue capped by tightening Dutch/US controls. - **Key technical assumption:** EUV remains a single-source monopoly — Zeiss optics, Cymer/TRUMPF source, ~5,000-supplier integration — that no rival can replicate this decade. Nikon/Canon and Intel tried EUV and gave up. - **Falsifier:** A credible second EUV source reaches leading-edge volume (Canon nanoimprint, or a Chinese SMEE EUV milestone — currently remote); OR leading-edge scaling stalls so High-NA adoption is deferred materially; OR a sustained down-cycle in net EUV bookings proves demand is less structural than the monopoly narrative assumes. - **Lead indicator to watch:** net new system bookings (EUV + High-NA) and service-revenue mix. ## AMD — ★★ (grounded: L16) - **Bull:** The only credible #2 accelerator. Silicon is at parity and AMD *leads on HBM capacity* generation after generation (MI300X 192 GB, MI350X 288 GB vs B200 192 GB) — winning where memory capacity is the constraint (large / long-context inference, served in fewer GPUs = better TCO). The wedge is inference, the fastest-growing segment, where the CUDA moat is thinnest (PyTorch/vLLM/Triton abstractions). Hyperscalers actively fund a second source (Meta serves Llama on MI300X; Azure/Oracle offer it); data-center GPU revenue ~$0→~$5B in 2024. Open standards (UALink, Ultra Ethernet) are a collective assault on NVIDIA's interconnect moats. - **Bear:** Lacks a *shipping* rack-scale NVSwitch equivalent — Infinity Fabric caps TP at ~8 GPUs/node, so large training still favors NVIDIA. ROCm trails ~15–20% on realized utilization and on stability. Distant #2 share; execution- and roadmap-dependent. - **Key technical assumption:** Inference (memory-bound, often single-node) is a large, fast- growing pool where the topology moat matters less and AMD competes on HBM capacity + price, with ROCm "good enough" via PyTorch/Triton. - **Falsifier:** *Bull confirmed* if AMD ships a qualified, rack-scale Helios/UALink fabric adopted at volume by a major hyperscaler AND ROCm reaches near-parity in production serving. *Bull broken* if AMD fails to gain material inference share despite competitive specs (moat holds regardless of silicon). - **Catalyst to watch:** 2026 — Helios MI400 rack + UALink qualification vs NVIDIA's Rubin gen. - **LIVE READ (CES 2026, decoded L26):** AMD unveiled the **Helios rack** (72× MI455X, HBM4, ~31 TB / 1.4 PB/s, ~2.9 EF FP4 inference / 1.4 EF FP8 training; MI400 family on track for 2H 2026). This is AMD's **first rack-scale scale-up domain** — but scale-up runs over **UALink-over-Ethernet, not an NVLink-class switched fabric**. So the NVDA topology falsifier is now **APPROACHING, not triggered** (the "qualified, switched, at-volume, hyperscaler" bar is unmet) and the HBM-capacity wedge is **reinforced**. Conviction +1 notch; **independence unchanged** (still capex-beta + the internal AMD↔NVDA share-shift hedge). **Next signal:** a named hyperscaler committing Helios/MI455X *for training* at volume **AND** an independent ROCm-vs-CUDA production benchmark inside ~5–10%. Sources: Tom's Hardware, NextPlatform (Jan/Feb 2026). ## Cadence / Synopsys — ★★★ (grounded: L18) - **Bull:** Two-player oligopoly (Cadence + Synopsys; Siemens EDA #3) on the software that *compiles* every chip from RTL to GDSII — the toll booth every design on earth must pass, including NVIDIA, AMD, Google TPU, and every Broadcom/hyperscaler ASIC. Switching costs are near- absolute (per-node PDK co-certification with each foundry + accumulated flows/IP/trained engineers). Subscription-heavy, high-margin, predictable recurring revenue. Two growth engines: AI-assisted design (DSO.ai / Cerebrus) and IP licensing (Synopsys interface IP; + Ansys multiphysics). The custom-ASIC boom is a *tailwind* (more design teams = more seats). - **Bear:** Core market growth is mature, tied to industry R&D / design starts. Advanced-node EDA is export-restricted to China (revenue cap + policy risk). Open-source flows (OpenROAD) a long- tail threat, far from advanced-node production parity today. - **Key technical assumption:** Switching costs + the two-player structure are durable because every advanced node ships with co-certified incumbent tool support; no third/open-source flow reaches leading-edge production parity. - **Falsifier:** A credible third platform or open-source flow wins *production* tape-outs at an advanced node; OR a major customer cohort in-sources design tooling; OR a structural decline in design starts / R&D budgets breaks the complexity-driven growth story. - **Lead indicator to watch:** recurring-revenue %, backlog/renewals, and design-start activity. --- ### Cross-cutting: which $/Mtok lever does each name own? (added L21) Inference serving cost = (cost/GPU-hr ÷ tokens/hr). Three levers move it; map each name to a lever and ask *how copyable* the edge is — that's the durability test for the inference-demand thesis. - **Throughput** (batching, FP8/FP4, MoE, spec-decode): NVDA software + the model lab. *Copyable in months → feature, not moat.* - **HBM bandwidth/capacity** (lifts the memory-bound ceiling, fits model in fewer GPUs): SK Hynix; AMD's capacity wedge. *Structural while HBM is supply-constrained.* - **$/GPU-hr** (own vs rent, ASICs, low PUE): AVGO (custom ASIC for high, stable volume); utilities/ cooling (L20 power). *Most durable — owning cheaper silicon + power at high utilization.* - **Build-vs-buy line** is the quantitative form of the AVGO ASIC-TAM falsifier (own wins at high stable util) and the AMD inference-wedge falsifier (memory-bound segment). MaaS margin = (sell − serve)/sell; price deflation (~$20→$0.40/Mtok, 2022→26) is a demand engine, not a bear signal. See [[0023-inference-unit-economics-lesson21]]. **Mechanism behind the levers (added L22):** inference = two phases — *prefill* (compute-bound, parallel, = cheap input tokens) and *decode* (memory-bandwidth-bound, sequential, re-streams all weights/token, = expensive output tokens, ~5:1 price ratio). The *KV cache* (grows with context × batch) — not the weights — caps concurrent users and thus throughput. So **HBM bandwidth + capacity is the binding inference lever, not FLOPS** → cleanest read-through to SK Hynix (both axes) and AMD (capacity wedge = KV-wall relief). Long-context + agentic/reasoning traffic shifts demand toward decode + KV → favors HBM capacity. Per name, ask: *which corner of the latency–throughput–cost triangle, and which side of the prefill/decode split, does its hardware win — and is that where volume is going?* See [[0024-inference-engine-deepdive-lesson22]]. --- ## Portfolio construction (L23 — the finale) — this doc IS the portfolio **Sizing rule:** `position size = conviction × falsifier-independence`. Conviction is the ★ field; independence is read off the falsifiers below — *how unrelated is what would break this name from what would break the rest?* Sizing on conviction × **upside** is the trap: it concentrates the book on the one shared factor. **The shared factor:** all seven names are differently-shaped claims on **hyperscaler AI capex**. So owning all seven ≈ ~1.5 *effective* bets, not seven — they draw down together on a capex air-pocket. Correlation, not name count, sets real diversification. **Falsifier-correlation clusters (the independence map):** - *Capex-air-pocket* (NVDA · SK Hynix · TSMC) — closest to pure capex beta; highly correlated. - *Design-starts* (ASML · Cadence/Synopsys) — same capex, lagged + service-cushioned. - *Share-shift* (AMD ↔ NVDA · AVGO) — partly an INTERNAL hedge (AMD bull = NVDA bear), not new independence across the factor. - *Orthogonal — power leg* (utilities/IPPs · cooling · SMR, from L20) — trips on grid/energy, NOT capex mix. The **only genuinely independent falsifier** → the real diversifier. Size it for the independence it adds, not its standalone upside. **Tier sizing (same identity, different binding):** toll booths (ASML/EDA/TSMC) sized UP for durability; leaders (NVDA/AVGO/AMD) sized to conviction but CAPPED (highest capex beta + competition falsifiers); SK Hynix sized SMALL + cycle-aware (dodge the L24 double-count); power leg sized as the hedge. Illustrative book (teaching artifact, not advice): Toll 40 / Leaders 35 / Cyclical 10 / Power 15. See [[0028-portfolio-synthesis-lesson25]]. ### How to use this doc - Before each new lesson, re-read the relevant name's **falsifier** and ask: *did anything this quarter move toward it?* - After each lesson, update the affected names and bump conviction (★) if the evidence shifted. - At capstone (L23), this doc *is* the portfolio thesis — sized by conviction and by how independent each name's falsifier is from the others. The per-name falsifiers above ARE the **quarterly watch-list**: one tripwire each, checked every earnings season.