You've built the knowledge. This is the skill that turns it into money: taking any real chip or AI announcement — a launch, an earnings call, an export rule — and decoding it the same disciplined way every time, ending where it matters: did a thesis falsifier just move?
Builds on: the whole course + THESIS.mdSkill: decode any announcement into a falsifier check
Every name in THESIS.md has a falsifier — the specific, observable signal that would force you to change your mind. Announcements are how the world delivers those signals. But they arrive wrapped in marketing, benchmarked against flattering baselines, and timed for maximum narrative. The investor's edge is not knowing more than the press release — it's having a fixed loop that strips the spin and ends on the only question that matters for your book.
retrievalL16 / L18
Before reading on, from memory: state NVIDIA's NVSwitch topology falsifier — the specific thing a competitor would have to do for you to conclude the rack-scale interconnect moat has broken. (We're about to test it against a real 2026 announcement.)
Answer
AMD (or anyone) ships a qualified, rack-scale NVSwitch equivalent adopted at volume by a major hyperscaler — i.e. an NVLink-class switched fabric enabling large tensor-parallel domains, not just point-to-point links. (Related: ROCm reaching CUDA throughput parity in production; ASIC mix displacing material training/inference volume.) Hold this exact wording — the AMD Helios reveal below is graded against it.
Core thesis: An announcement is worthless until it's been run through a loop that ends in a position. The loop is five steps — Strip → Mechanism → Falsifier → Sizing → Next signal — and step 3 is the one analysts skip. Most reactions stop at "is the spec good?" Yours stops at "which falsifier did this move, and by how much?" That single habit is the difference between consuming news and updating a thesis.
01 — Why a Loop, Not a Take
The Discipline Is the Edge
Announcements are engineered to produce a feeling — awe, fear, FOMO. A loop replaces the feeling with a procedure, which does three things a hot take can't: it's repeatable (same rigor at 11pm on a surprise 8-K as on a planned keynote), it's comparable (you can line up AMD's claim against NVIDIA's because you stripped both the same way), and it's falsifiable (it forces you to say in advance what would change your mind, so you can't rationalize after the fact). You already did the hard part — you wrote the falsifiers. The loop just makes sure every piece of news gets checked against them.
02 — The Decode Loop
Five Steps, Every Time
STRIP → MECHANISM → FALSIFIER → SIZING → NEXT SIGNAL
Steps 1–2 are technical (is the claim real?). Steps 3–4 are the investor lens (does my book change?). Step 5 keeps the thesis alive between announcements.
StripSeparate the claim from the marketing.
Extract the literal number, then flag the spin: "up to" (best-case, not typical); the base of comparison (vs which prior gen? which competitor? one gen or two?); the precision regime (FP4 doubles the FLOPS of FP8 — never compare across precisions); peak vs sustained; roadmap vs shipping; and the unit (per-chip, per-rack, or system-level token cost?).
MechanismWhat physical lever produced the gain — and what was traded away?
Real gains come from a lever you've studied: more HBM (capacity/bandwidth), lower precision, a bigger die, better interconnect, or a packaging/process step. Name the lever, then name the omission — power, yield, generality, or a missing part of the stack. "Real but framed" is the most common verdict.
FalsifierWhich name does this touch, and which THESIS.md falsifier did it move?
Open THESIS.md. For each name implicated, ask: did this push a falsifier toward triggering, approaching, or receding? Be precise — match the announcement against the exact wording of the falsifier. Most news approaches a falsifier; rarely does one announcement trigger it.
SizingDoes conviction or independence change?
Recall the rule: size = conviction × falsifier-independence. Ask whether this moves the ★ conviction (a notch, usually) or — much rarer and more important — the independence of a name's falsifier from the rest of the book. Reinforcing the shared AI-capex factor changes conviction, not diversification.
Next signalWhat single observable confirms or denies next?
End every decode by naming the one thing to watch next quarter that would resolve the falsifier — then add it to the watch-list. This converts a one-off reaction into a standing monitoring rule and prevents the announcement from fading into vibes.
The cleanest possible test: a real announcement that maps directly onto a falsifier you pre-registered. At CES 2026 (Jan), AMD detailed the Helios rack — 72× Instinct MI455X, HBM4, ~31 TB aggregate memory at ~1.4 PB/s, ~2.9 EF FP4 inference / ~1.4 EF FP8 training per rack — with the MI400 family "on track for 2H 2026." Scale-up uses UALink-over-Ethernet (the open standard), which reviewers noted "could hamstring performance" versus a switched fabric. [Tom's Hardware][NextPlatform]
Step
The decode
Strip
Headline EFs are FP4 (inference) — the like-for-like training number is 1.4 EF FP8. "On track for 2H 2026" = roadmap, not shipping. The genuinely new fact isn't the FLOPS — it's that AMD now has a 72-GPU rack-scale scale-up domain, its first real answer to NVL72.
Mechanism
Two real levers: HBM4 capacity (the AMD wedge continues — memory capacity lead generation over generation) and a rack-scale design. The omission is the crux: scale-up runs over UALink-over-Ethernet, not an NVLink-class switched fabric. Ethernet adds latency/overhead exactly where it hurts most — the per-layer all-reduce of large tensor-parallel training. Also unproven: ROCm production parity and hyperscaler qualification.
Falsifier
NVDA topology moat ("qualified, rack-scale NVSwitch equivalent adopted at volume by a hyperscaler"): AMD now has a rack-scale design → approaching — but not triggered (UALink-over-Ethernet ≠ NVLink-class switched fabric; "qualified + at volume + hyperscaler" unmet). AMD bull ("ships qualified rack-scale Helios/UALink at volume AND ROCm near-parity"): silicon + rack exist; qualification, volume, and ROCm legs unproven → approaching. SK Hynix / AMD HBM wedge: HBM4 capacity reinforces the memory-capacity thesis → recedes (bullish HBM; bear case further away).
Sizing
AMD ★ conviction +1 notch — it has a credible rack-scale roadmap, no longer node-capped at ~8 GPUs on paper. Independence unchanged: still rides the same AI-capex factor; still the internal AMD↔NVDA share-shift hedge, not a new orthogonal bet. NVDA topology conviction intact today, but the falsifier is now live — the clock started.
Next signal
A named hyperscaler committing Helios/MI455X at volume for training (not just inference) plus an independent ROCm-vs-CUDA production benchmark inside ~5–10%. Until both appear, the NVSwitch topology moat holds and AMD's win stays an inference-capacity story.
The payoff of step 3: a headline reader sees "AMD challenges NVIDIA's rack" and either panics on NVDA or chases AMD. You see a falsifier move from dormant to live-but-not-triggered, nudge one conviction by a notch, change zero position sizes today, and write down the exact two events that would change them. That is the whole game.
04 — Foil: Reading the Other Side
NVIDIA Vera Rubin & the Groq Buy — A Fast Pass
At GTC 2026 NVIDIA unveiled Vera Rubin, claiming "up to 10× lower inference token cost vs Blackwell," with AWS/Azure/Google/Oracle as first deployers; it also disclosed a ~$20B Groq acquisition. [CNBC] Run the loop fast:
Strip: "up to," vs Blackwell (one-gen base), token cost (system-level, not per-chip), inference (not training). A best-case system number, not a chip spec.
Mechanism: stacked levers — FP4, more HBM, better interconnect, disaggregated serving. Real, but the 10× is the favorable corner of the design space.
Falsifier: reinforces NVDA's "extends the lead into production inference" — and pushes AMD's inference wedge the wrong way (harder to win on $/token if NVIDIA cuts it 10×). The Groq buy = NVIDIA hedging the inference-ASIC threat in-house → a small read-through to the AVGO ASIC-TAM falsifier (the giant is defending that turf).
Sizing / Next: NVDA inference conviction firms a notch; watch whether the 10× shows up in real serving $/Mtok (L21/L22 math), not slideware.
05 — Your Turn: Self-Grader
Decode a Live One — Then Check Yourself
The exercise (do this from memory). Announcement: NVIDIA Q1 FY27 earnings (May 2026) — record revenue $81.6B (+85% YoY), Data Center $75.2B (+92% YoY). [NVIDIA 8-K] Write your own five-step decode before revealing each model answer. Effortful retrieval is the point — peeking first wastes the rep.
step 1strip
What do you strip away — and what's the number that actually carries the thesis signal here?
Model answer "Record" is backward-looking; raw revenue growth is mostly supply catching up to known demand. The signal that carries the thesis isn't the top line — it's the gross-margin trend and the sequential DC trajectory. Strip to: "is margin holding, and is growth decelerating?"
step 2mechanism
What's the mechanism behind the number — what is actually binding?
Model answer Demand still vastly exceeds supply, so reported revenue ≈ what NVIDIA can ship. The binding constraint is upstream — CoWoS packaging, HBM, and increasingly power — not end-demand. Revenue is a supply read, not a demand read.
step 3falsifier
Which falsifiers does this touch — and did any move?
Model answer +92% DC means the capex-air-pocket falsifier (NVDA/TSMC/SK Hynix) is receding — no demand cliff this quarter. The live one is NVDA's competition falsifier: watch the gross-margin trend — erosion toward the low-60s would be the first hard sign ASIC/AMD pressure is biting, visible in financials before the narrative.
step 4sizing
Does this change conviction or independence?
Model answer One strong print barely moves conviction and moves independence not at all — it reinforces the shared capex factor that already binds the book together. Trends move convictions; single beats don't. If anything, a blowout that's all capex-beta is a reminder the seven names still ≈ one bet.
step 5next signal
What's the single observable to watch next?
Model answer The gross-margin trajectory over the next 2–3 quarters, plus management's language on whether power/interconnect is now the binding constraint, and the hyperscaler capex guides. Margin direction is the earliest tradable signal of the competition falsifier.
06 — Common Traps
Where the Loop Saves You
The precision switcheroo
FP4 numbers compared to a rival's FP8 (or to last gen's dense FLOPS) inflate a "lead" by 2× before any real work. Step 1 forces like-for-like; if the precision isn't stated, treat the number as marketing until it is.
Roadmap mistaken for shipping
"On track for 2H," "sampling," "announced" — none of these is volume revenue. A falsifier that needs "at volume, qualified by a hyperscaler" cannot be triggered by a keynote. Date the claim before you act on it.
Spec win ≠ thesis win
A better number that doesn't touch a falsifier is noise for your book. Conversely a mediocre spec that does (a hyperscaler qualifying a second source) is a major event. Step 3 is what separates the two.
Confusing conviction with independence
Most good news raises conviction on a name that's already correlated with the rest of the book — which barely improves the portfolio. Only news that moves a falsifier's independence (e.g. the power leg) changes real diversification. Size to that.
Primary Source
Go Deeper
Read first: go to the primary document every time — the company's own earnings release / 8-K and keynote, not the headline about it. Pair with a teardown shop that strips the spin for a living: SemiAnalysis and Tom's Hardware for the technical read (both in RESOURCES.md). The skill is reading the primary source first, forming your decode, then checking it against the teardown — not the reverse.
Comprehension Check
Quiz — 6 Questions
Select the best answer for each.
1. In the decode loop, which step is the one most analysts skip?
Stripping the marketing language from the literal claim
Mapping the news onto a specific pre-written falsifier
Identifying the physical lever behind the performance
Naming the single signal to watch the next quarter
2. AMD's Helios rack at CES 2026 mainly mattered because it:
Shipped a switched NVLink-class fabric at hyperscaler volume
Gave AMD its first rack-scale scale-up domain on paper
Proved ROCm had reached full CUDA production parity
Showed FP8 training FLOPS far beyond any NVIDIA rack
3. Why did Helios bring NVIDIA's topology falsifier to "approaching" but not "triggered"?
UALink-over-Ethernet is not a qualified switched fabric at volume
AMD has no high-bandwidth memory on the MI455X accelerator
NVIDIA had already discontinued its own NVSwitch fabric
The rack used fewer GPUs than a comparable NVL72 system
4. A vendor cites "up to 10× lower token cost vs last gen." The first thing to flag is:
That token cost can never be measured in real serving systems
"Up to," the one-gen base, and that it's a system-level claim
That lower cost always signals weakening end-market demand
That inference cost is irrelevant to any investment thesis
5. In an NVIDIA earnings print, the earliest tradable sign of competition biting is:
A single quarter of decelerating headline revenue growth
A sustained downtrend in data-center gross margin
A rise in absolute research-and-development spending
An increase in the total addressable market estimate
6. Good news that only raises conviction on an already-correlated name mainly:
Improves the portfolio's real diversification substantially
Leaves effective-bet count roughly unchanged despite the lift
Triggers the falsifier for every other name in the book
Proves the shared underlying factor has been eliminated
From your instructor: The frame to keep — Strip → Mechanism → Falsifier → Sizing → Next signal; the falsifier step is the edge; most news approaches a falsifier, rarely triggers one; raise conviction freely but change independence almost never. THESIS.md is now a live tripwire system — every announcement gets decoded against it. Ask me anything, or better: bring me a real announcement from this week and we'll run the loop together and update THESIS.md live. (Still open whenever you want them: the overdue spaced re-tests of your shaky Checkpoint 2 & 3 cards — just tell me which.)