Advanced packaging is the fastest-growing and least-understood part of the semiconductor
value chain. It is where TSMC earns an increasingly large share of its revenue, where the
performance gains of modern AI chips actually come from, and where a distinct set of
investment plays — substrates, bonding equipment, OSATs — live outside the usual
semiconductor stocks. Lesson 4 gave you CoWoS in the context of TSMC. This lesson gives
you the full landscape.
Part 1 — Why Packaging Became the New Frontier
The end of "all performance comes from transistors"
Until roughly 2015, improving a chip's performance meant one thing: shrink the transistors.
Smaller transistors → denser packing → shorter wires → faster signals. This was Moore's Law.
The entire industry — EDA tools, IP libraries, customer product roadmaps — was structured around
this assumption.
Three things broke the assumption simultaneously:
Node economics. Each generation of shrink became exponentially more expensive
to develop and manufacture. A leading-edge fab cost $10B in 2010; it costs $20B+ today.
Fewer companies can afford to build one. This drove fabless chip design but also raised the
threshold for when a new node makes economic sense.
The memory wall. Compute performance scaled 3× faster than memory bandwidth
over the last decade. A chip can do far more arithmetic than it can fetch data to work on.
Shrinking transistors improves compute but doesn't fix the memory bottleneck — you need
to rethink where the memory lives relative to the compute.
The yield wall for large dies. A single 800mm² die at leading-edge nodes
has 40–55% yield. But if you could make 4 × 200mm² dies and assemble them, each would
yield 80%+. The packaging challenge — how to connect multiple smaller dies as if they
were one — became as valuable as the node challenge itself.
The "More than Moore" insight
The semiconductor industry coined "More than Moore" to describe getting more system
performance without (only) shrinking transistors. Advanced packaging is the primary vector:
stack the memory on the compute die, integrate chiplets at silicon-like density, mix
different process nodes in one package. A chip built this way in 2025 can outperform a
hypothetical monolithic die at 1nm — at lower cost and better yield.
NVIDIA Blackwell's two-die + 8× HBM3E configuration is not a transitional hack.
It is the permanent architecture of frontier AI chips.
Part 2 — The Full Advanced Packaging Taxonomy
2D → 2.5D → 3D → Wafer-to-Wafer: what each means
2D — Traditional
Flip-Chip on Substrate
Single die placed on organic substrate with C4 solder bumps. Everything in one plane. Substrate routes signals to PCB below. Die sizes limited by reticle. No die-to-die integration.
Examples: Intel Core (pre-chiplet), Qualcomm Snapdragon 8 Gen 1
2.5D — Interposer
CoWoS / Si Interposer
Multiple dies placed side-by-side on a silicon or RDL interposer. Dense die-to-die wiring at sub-μm pitch. Memory (HBM) lives adjacent to compute die. No vertical stacking of active dies.
Examples: NVIDIA H100/B200, AMD MI300X, Google TPU v5
3D — Die Stacking
SoIC / Foveros / V-Cache
One active die physically on top of another. Vertical connections via TSVs or hybrid bonds. Eliminates all wire length for stacked die pair. Heat dissipation is the main constraint.
Examples: AMD Ryzen 3D V-Cache, TSMC SoIC, Intel Foveros, Sony CIS sensors
W2W — Wafer-to-Wafer
Whole-Wafer Bonding
Entire 300mm wafers bonded together before dicing. Requires ±100nm alignment across the full wafer — 5× tighter than die-to-wafer. Highest bond density possible. Only viable if die sizes and defect maps align.
Examples: Sony BSI CMOS sensors, Apple rumored future, research at imec
The integration density progression
The key metric across these tiers is how many connections per mm² you can make between dies.
Traditional FC-BGA: ~1 connection/mm². CoWoS Si interposer: ~100–1,000 connections/mm².
SoIC hybrid bonding (9μm pitch): ~12,000 connections/mm². W2W hybrid bonding (1μm pitch, future):
~1,000,000 connections/mm². Higher density = shorter wires = more bandwidth = lower power per bit.
Part 3 — TSMC InFO: The Mobile Packaging Revolution
How Apple's iPhone 7 changed packaging forever in 2016
Before diving into CoWoS and SoIC, InFO deserves its own treatment — it is TSMC's first
major advanced packaging innovation, and it won Apple's A10 chip business in 2016 based
purely on packaging performance, not node superiority.
InFO stands for Integrated Fan-Out. "Fan-out" means the die's IO pins
extend beyond the die's own footprint using redistribution layers (RDLs) built in mold
compound around the die — rather than on an organic substrate beneath it.
Traditional Flip-Chip BGA
Package thickness: ~1.3mm
Substrate is the dominant thickness contributor (~0.7mm) and cost.
Signal must travel die → C4 bump → substrate → BGA ball → PCB.
Each substrate layer adds parasitic inductance + resistance.
Substrate vendors (Ibiden, Shinko) are a separate supply chain dependency.
TSMC InFO (Integrated Fan-Out)
Package thickness: ~0.6mm — 2× thinner
TSMC builds RDL layers directly over the die using wafer-fab equipment (lithography, deposition).
No substrate needed. Die IO "fans out" across the mold compound area using fine copper traces.
Result: half the thickness, lower cost, better electrical performance.
Apple switched A10 to InFO in 2016; all A-series chips since have used InFO.
[EE Times — TSMC InFO]
InFO variants have since expanded: InFO-PoP (Package-on-Package — stacks
a DRAM package on top of the InFO AP chip, used in all iPhone since 2016),
InFO-oS (on substrate — hybrid approach for larger chips requiring substrate-level
IO density), and InFO-SoIC (integrates InFO fan-out with 3D die stacking).
InFO is now TSMC's highest-volume advanced packaging technology by unit count.
Part 4 — CoWoS: The 2.5D Platform (Deep Technical in L04)
Three variants, one purpose: bring memory and compute millimeters apart
Lesson 4 covers CoWoS in full technical depth (variants S/R/L, HBM TSV architecture,
bandwidth math, compound yield, assembly process). Here we focus on what the three variants
trade off and why the variant choice matters as much as the underlying silicon node.
CoWoS variant selection — decision map
CoWoS-S is density-first but size-limited. CoWoS-R is size-first but density-limited.
CoWoS-L achieves both by using silicon bridge tiles only where needed and
organic substrate elsewhere — the EMIB concept (Intel pioneered) taken to larger scale.
NVIDIA chose CoWoS-L for Blackwell because no other packaging platform can support
two 800mm² GPU dies + 8 HBM stacks in one coherent electrical package.
Part 5 — SoIC: True 3D Stacking with Hybrid Bonding
What happens when the gap between two dies goes from 15μm to zero
CoWoS places dies side-by-side on an interposer — they're in the same horizontal plane.
SoIC (System on Integrated Chips) places one active die directly on top
of another. The difference is not just geometric — it changes every electrical property
of the die-to-die connection.
The solder micro-bump limit — why we needed a new bonding method
Thermo-compression bonding (TCB) with Cu-pillar + solder micro-bumps works well at
10–40μm pitch. But below ~6μm pitch, solder bridging becomes a yield killer — adjacent
bumps short-circuit when molten solder spreads. And even at 10μm pitch, each bump has a
15–20μm "standoff height" — a physical gap between the dies filled with underfill epoxy.
That gap means signal wires between dies are 15–20μm long — not zero.
Hybrid bonding eliminates bumps entirely. Two polished copper surfaces
are brought into contact at room temperature (van der Waals forces hold them), then
annealed at 200–300°C. The copper atoms diffuse across the interface and form a continuous
metallic bond — no solder, no underfill, no standoff height. The result: die-to-die copper
connections with essentially zero gap, at pitches as small as 1μm (research) or
9μm (production at TSMC SoIC-X today).
Bond pitch evolution — how the density will grow
2016
Cu pillar + solder
micro-bump TCB
40μm
625 /mm²
2022
CoWoS TCB
thermo-compression
10μm
10,000 /mm²
2022
SoIC-X (TSMC)
hybrid bonding
9μm
12,346 /mm²
2024
SoIC-X (gen 2)
hybrid bonding
4.5μm
49,000 /mm²
2026E
SoIC next-gen
hybrid bonding
3μm
111,000 /mm²
2028+
Research / W2W
hybrid W2W
1μm
1M /mm²
Bar = relative pitch (wider = coarser). Connections/mm² = (1000/pitch)². At 1μm pitch: 10⁶ connections/mm² — approaching transistor density.
SoIC-X vs SoIC-Y: which face is up
SoIC-X — Face-to-Face
Active surfaces bonded directly together
Top and bottom dies face each other. Provides the shortest possible die-to-die wire. Used for AMD 3D V-Cache (SRAM on top of CPU). Requires very precise bonding alignment since active circuits are touching.
SoIC-Y — Face-to-Back
Top die's active face bonds to bottom die's backside
Top die's active face bonds to the bottom die's silicon backside (via TSVs). Bottom die's active surface still faces down toward the substrate. More flexible IO routing. Used when the top die also needs its own connections to the outside world.
AMD 3D V-Cache: the commercial proof of SoIC-class technology
Why AMD's V-Cache matters as a technical proof point
In 2022, AMD launched the Ryzen 7 5800X3D: a Zen 3 CPU with 64MB of SRAM die stacked
on top using hybrid bonding (TSMC SoIC at ~9μm pitch). The SRAM die bonds directly to
the CPU die's active surface. Result: 200 GB/s bandwidth between L3 cache and CPU cores
— vs. ~32 GB/s for in-die L3 cache that's next to (but not on top of) the cores.
Gaming benchmarks improved 15% vs. the non-3D variant at the same clock speed.
This is not about raw compute — it is entirely about bandwidth and latency from memory
proximity. The chip proved that 3D stacking with hybrid bonding could reach volume
production with good yield and thermal management. It is the reference design that
convinced the industry that SoIC is real, not just research.
[3D V-Cache technical review]
Part 6 — Heat: The Hard Physics Limit on 3D Stacking
Why you can't just stack 10 chiplets on top of each other
Every watt of power dissipated in a chip must travel somewhere as heat. In a 2D chip,
heat spreads laterally through the silicon and upward through the IHS (integrated heat
spreader) to the cooler. In a 3D stack, heat generated in lower dies must travel
through upper dies before it can escape — and silicon is not a great thermal conductor.
149 W/m·K
Silicon thermal conductivity
Copper is 385 W/m·K. Silicon is 4× worse. In a 3D stack with 50μm-thick dies, thermal resistance between bottom die and cooler (top of stack) scales linearly with die count. A 4-die stack has 4× the thermal resistance of a single die — at the same power density.
1.25 W/mm²
Typical AI chip power density
B200: ~1,000W over ~800mm² = 1.25 W/mm². For context, the sun's surface emits 0.063 W/mm². Power density of AI chips exceeds nuclear reactor fuel rod averages. This level of heat flux simply cannot route through a second silicon die — the junction temperature would exceed the safe operating range.
~2 dies
Practical 3D stack limit for high-power logic
For power-hungry dies (CPU, GPU), practical 3D stacking is currently limited to 2 active logic dies before thermal management becomes intractable. AMD V-Cache works because SRAM dissipates very little power per mm². You can stack low-power memory or cache dies on top of high-power compute dies — but not two high-power compute dies.
12-high
Why HBM can stack 12 DRAM dies
DRAM at rest dissipates ~0.2 W/mm² — 6× less than compute logic. The HBM stack's total power is modest. Combined with active cooling of the HBM stack (vapor chamber, direct liquid cooling), 12-die stacks are thermally manageable. This is why memory stacking is far ahead of logic stacking in die count.
The research direction: backside cooling for 3D stacks
The frontier solution: remove silicon from the back of the bottom die (leave only the active
transistor layer + BEOL) and attach a microfluidic cooling channel directly to it. IBM,
imec, and TSMC have all demonstrated this in research. It would allow liquid cooling to
reach within micrometers of the transistors — potentially enabling 4–8 high-power logic
die stacks. The manufacturing challenge is extreme: thinning a die to 5–10μm (it becomes
fragile as paper) and handling it without breaking. Not production-ready today.
Part 7 — The Chiplet Paradigm: Yield Math and Node Mixing
Why splitting a large die into small ones is both economically and technically superior
The yield math — why smaller dies yield better
Chip yield is governed by the Poisson defect model. If the average defect density on a
wafer is D defects/cm², and a die has area A (cm²), the probability that a die has zero
defects (and therefore works) is:
Simplified yield model: Y ≈ e−A·D
D = 0.10 defects/cm² (typical leading-edge new node)
Monolithic 800mm² GPU (single die): Y = e^(−0.80) = 45% Split into 4 × 200mm² chiplets: each Y = e^(−0.20) = 82% All 4 needed (compound yield): 0.82⁴ = 45% ← same package yield
BUT: monolithic 800mm² wafer cost: $10,000 / ~9 good dies = $1,111/chip Chiplet: 200mm² wafer cost: $10,000 / ~65 good dies × 4 = $615/chip
The cost advantage: a defect in one 200mm² chiplet scraps that chiplet ($152 value).
A defect in the same location in an 800mm² monolithic die scraps the whole die ($1,111 value).
With Known Good Die (KGD) testing before assembly, bad chiplets never enter the package.
The monolithic die has no equivalent recovery path — one defect anywhere = full die loss.
Node mixing — the second chiplet advantage
A monolithic die must be manufactured entirely on one process node. With chiplets, each
component can be optimized independently:
Compute cores: N3/N2 — most advanced node for performance
SRAM cache: N5 — SRAM scales worse than logic; N3 SRAM is expensive for marginal benefit
Analog / SerDes / PHY: 28nm or 16nm — analog circuits don't benefit from advanced nodes; older node = more stable, less leakage
IO / USB / PCIe controllers: 7nm/5nm — adequate, much cheaper than N3
AMD EPYC as the chiplet yield proof
AMD's EPYC (server) processors since 2017 (Naples) use chiplets: multiple 8-core Zen dies
("Core Complex Dies" or CCDs) connected to a central I/O die. EPYC Genoa (2022) has 12 × 5nm
compute CCDs + 1 × 6nm I/O die. The I/O die (large, with lots of SerDes and memory controllers)
uses an older, cheaper node. The compute CCDs (small, dense) use the leading node.
This split lets AMD manufacture 96-core server CPUs that Intel couldn't match with a
monolithic approach — Intel's equivalent monolithic die would yield below 30%.
AMD's chiplet approach achieves better yield at lower cost at higher core count.
It is the reason Intel lost server market share from 2017–2023.
[AnandTech AMD chiplet analysis]
The chiplet standards problem — UCIe
The bottleneck for chiplet adoption beyond AMD/Intel/Apple: chiplets from different vendors
can't connect to each other without a common interconnect standard. Each company has been
using proprietary interfaces (AMD's Infinity Fabric, Intel's EMIB protocol, Apple's
UltraFusion). UCIe (Universal Chiplet Interconnect Express) — launched 2022,
backed by Intel, AMD, TSMC, ARM, Qualcomm, Samsung — aims to standardize the die-to-die
interface so chiplets from vendor A can connect to a package from vendor B.
UCIe 1.0: 16 Gbps per lane, up to 28 TB/s bandwidth per mm of interface width at 2μm bump pitch.
Wide adoption would unlock a chiplet marketplace — buy a CPU compute die from AMD, a GPU
from NVIDIA, a memory controller from Marvell, and assemble them on a TSMC CoWoS interposer.
This is not yet a reality but is where the industry is structurally heading.
Part 8 — The Packaging Ecosystem
Who makes what — and where the investable plays are
Layer
Company / Companies
What they supply
Moat type
Investment note
Assembly (leading-edge)
TSMC
CoWoS (S/R/L), InFO, SoIC — the actual bonding, interposer fab, wafer-level assembly
Monopoly
The only company doing all three at volume. Already covered in L04.
ASE Group (3711.TW): world's largest OSAT by revenue. Beneficiary of overall packaging growth but limited leading-edge exposure. Defensive, not high-growth.
Organic substrate
Ibiden, Shinko, AT&S, SEMCO
ABF (Ajinomoto Build-up Film) substrate: the organic package foundation. Ibiden + Shinko = ~55% of ABF substrate supply.
Duopoly
Ibiden (4062.T): pure-play substrate. Long lead times, multi-year capacity expansion cycles. Benefits from server/AI substrate demand surge. Cyclical but structurally growing. AT&S (ATS.VI): Austrian, growing share in datacenter substrates.
Bonding equipment
Besi (BE Semiconductor), Kulicke & Soffa
Thermo-compression bonding machines (TCB) and hybrid bonding systems. Every CoWoS line, every flip-chip line uses one of these.
Duopoly
Besi (BESI.AS) is the most direct pure-play on advanced packaging growth. ~80% share of advanced flip-chip and TCB machines. As CoWoS-L and SoIC scale, every new bonding tool is likely a Besi sale. Revenue highly cyclical (equipment purchasing in waves), but secular demand is clear.
Process equipment
AMAT, Lam Research, TEL
CVD/PVD for TSV copper fill, CMP for planarization of interposers, etch for TSV formation, electroplating.
Oligopoly
Packaging is a growing revenue segment for AMAT and Lam, but a small share of their total. Not pure-plays — advanced node silicon is still their primary market.
Inspection / metrology
Onto Innovation, Camtek
Post-bond inspection, bump measurement, overlay metrology for packaging. Checks that 10μm micro-bumps landed within ±0.5μm spec.
Competitive
Camtek (CAMT): growing rapidly with advanced packaging demand. Onto Innovation (ONTO): broader semiconductor inspection but growing packaging share. Both are relatively small-cap leverage plays on CoWoS expansion.
HBM memory
SK Hynix (~50%), Samsung (~30%), Micron (~20%)
HBM DRAM stacks with TSVs. Sole supply for AI GPU memory.
Oligopoly
SK Hynix (000660.KS): dominant HBM3E supplier, premium pricing power, but DRAM cyclicality. If SK Hynix has a yield or supply issue, NVIDIA can't ship B200s regardless of TSMC CoWoS capacity. Separate risk vector from TSMC.
Part 9 — Investment Map: The Advanced Packaging Value Chain
Where to play — and what each bet is actually on
~15–20%
TSMC packaging revenue 2026E
Growing from <5% in 2021
3.7×
CoWoS capacity ramp '24→'26
35K → 130K wafers/month
~80%
Besi share of advanced flip-chip bonding equipment
Near-monopoly on the critical tool
2027+
HBM4 ramp timeline
Next CoWoS upgrade cycle; 2048-bit bus
Tier 1 — Core position
TSMC (TSM / 2330.TW)
Packaging revenue growing fastest within TSMC. CoWoS-L and SoIC expansion gives TSMC a second monopoly adjacent to its silicon node moat. Each HBM generation upgrade (HBM4 in 2026–27) drives a CoWoS-L ramp that benefits TSMC directly in revenue and margin. Advanced packaging ASP is 30–50% higher per wafer than silicon-only processing at equivalent node.
TSM · TWD denominated via ADR: TWD/USD exposure
Tier 1 — Equipment pure-play
Besi / BE Semiconductor (BESI.AS)
The most direct publicly traded lever on advanced packaging growth. ~80% market share in thermo-compression bonding machines for advanced flip-chip and CoWoS. Every new CoWoS-L line or SoIC line requires multiple Besi machines. Revenue is lumpy (equipment ordering in batches) but secular demand from AI packaging is clear. Dutch-listed, small-mid cap, high cyclicality.
BESI.AS · Amsterdam · ~€4–6B market cap range
Tier 2 — Substrate infrastructure
Ibiden (4062.T)
Japan's dominant ABF substrate manufacturer. Ibiden substrate goes into virtually every AI server chip package as the organic base layer. Supply is structurally tight — substrate capacity takes 2–3 years to expand (unlike equipment which can be ordered and installed faster). Beneficiary of the same AI infrastructure buildout as TSMC but at the materials/substrate layer.
4062.T · Tokyo · exposure to JPY
Tier 2 — HBM supply
SK Hynix (000660.KS)
Dominant HBM3E supplier (~50% share). Premium pricing relative to commodity DRAM. The AI chip supply chain cannot function without SK Hynix's HBM output. Risk: DRAM price cyclicality (HBM premium narrows when commodity DRAM weakens), and Samsung/Micron ramping to capture share. Also: single site concentration risk (Icheon fab).
000660.KS · Seoul · KRW exposure
Tier 3 — Small-cap leverage
Camtek (CAMT)
Israeli wafer inspection company with growing advanced packaging inspection revenue. Post-bond inspection for CoWoS and flip-chip is a required step TSMC performs on every wafer. Camtek's tools verify bump placement accuracy. Small cap ($2–3B), high growth, but limited moat vs. AMAT/KLA in the broader inspection market.
CAMT · NASDAQ · USD
Tier 3 — OSAT exposure
ASE Group (3711.TW / ASX)
World's largest outsourced assembly and test provider. Benefits from overall packaging volume growth. Does not compete at CoWoS-L / SoIC level — too capital-intensive and process-complexity-intensive for an OSAT. Defensive play: mature packaging grows with general semiconductor volume. Not a pure-play on the AI packaging wave.
3711.TW (Taiwan) / ASX (NYSE ADR)
The risk you don't hear about: China's packaging ambitions
China cannot replicate TSMC's N2 silicon node. But advanced packaging is an easier target:
the processes (flip-chip bonding, interposer fabrication at mature nodes) are less equipment-restricted.
Chinese packaging companies (JCET, Tongfu Microelectronics) are investing heavily in
advanced packaging, particularly for chips that don't need CoWoS-L (e.g., mid-range AI
chips at 7nm or 14nm on mature-node interposers). If China can package SMIC chips at
CoWoS-S class quality, the combination enables a self-sufficient AI chip pipeline.
This is a 2028–2030 risk, not imminent — but it's the most credible path for China
to partially circumvent the equipment-export constraint.
[SemiAnalysis — China packaging]
Practice Project — Package Configuration Selector
Given a chip design requirement, choose the right packaging approach. Select your constraints
below and the tool will recommend a configuration with reasoning. There are often
multiple valid answers — the reasoning matters more than the label.
Step 1 — Select your design parameters
Quick check — match the technology to its description
1. You are designing an AI chip that needs >8 TB/s memory bandwidth and has two 800mm² GPU compute dies. What packaging technology is required?
CoWoS-S (full silicon interposer)
CoWoS-L (local silicon bridge in organic substrate)
InFO (fan-out in mold compound)
Flip-chip BGA (organic substrate only)
2. AMD stacks 64MB of SRAM on top of a Zen 4 CPU die using hybrid bonding at 9μm pitch. What TSMC packaging technology is this?
CoWoS-S
InFO-PoP
SoIC-X (face-to-face hybrid bonding)
CoWoS-L
3. Apple's A17 Pro in iPhone 15 is thinner than the A15 package despite using a more complex 3nm process. What packaging technology makes this possible?
CoWoS-S (silicon interposer)
InFO-PoP (fan-out, no substrate)
SoIC (3D hybrid bonding)
Flip-chip on organic substrate
4. A startup wants to build an AI chip using SMIC's 7nm-class process (limited yield) and integrate it with HBM memory at 2 TB/s bandwidth. What packaging approach does NOT make sense, and why?
CoWoS-R (RDL interposer) — achieves needed bandwidth at reasonable cost
CoWoS-L (gold standard) — overkill for 2 TB/s; SMIC die yield will be the constraint, not packaging; the premium cost is unjustified
Flip-chip BGA with GDDR6 — can achieve ~1–1.5 TB/s, closer to the target without interposer cost
CoWoS-S — would work technically for 2 HBM stacks at 2 TB/s
5. Why can't engineers simply stack 6 high-power GPU dies vertically using hybrid bonding to get 6× the compute without any new lithography?
Hybrid bonding yield is too low — each bond layer would fail
The UCIe standard does not yet support 3D stacking
Thermal: heat from lower dies cannot escape through upper dies fast enough — junction temperatures exceed safe limits
TSMC's SoIC process is limited to 2μm pitch, not fine enough for GPU-class IO density
Lesson 6: NVIDIA and the CUDA moat — why 18 years of software lock-in matters more than GPU specs, and how AMD, Google, and Huawei are trying to break it
Lesson 7: The Transformer architecture from first principles — what self-attention actually computes, why it demands bandwidth over compute, and what that means for chip demand
Ask me anything. Good follow-ups:
"How does TSMC price CoWoS-L vs. CoWoS-S — what's the ASP premium?" ·
"What happens to Besi's revenue in a semiconductor downcycle?" ·
"How does the UCIe standard change TSMC's competitive position?" ·
"Walk me through the actual steps of hybrid bonding at TSMC's SoIC fab" ·
"How does China's JCET compare technically to TSMC's advanced packaging?"