Written for a tech worker who wants the real physics, and a long-term TSMC investor who
wants investment depth beyond headlines. The technical and investment lenses are woven together
throughout — because for TSMC, they are inseparable.
Part 1 — The Founding Insight
One idea. One promise. Thirty-seven years of compounding.
In 1987, Morris Chang was 56 years old. He had spent 25 years at Texas Instruments, rising to
group vice president — and been passed over for CEO. He had recently run General Instrument's
semiconductor division. Taiwan's Industrial Technology Research Institute had recruited him to
run the country's technology development.
The conventional wisdom in 1987: advanced chip manufacturing required being an IDM —
designing and building your own chips. Companies like Intel, TI, and Motorola did both.
This was considered necessary because manufacturing expertise fed back into design, and design
requirements shaped manufacturing.
Chang saw the flaw: an IDM that manufactured for outsiders was always a competitor
to those outsiders. No serious chip designer would hand their most sensitive IP to
a competitor's factory. This structural conflict meant IDMs had a ceiling as contract manufacturers.
The market for pure-play foundry services was large and completely unserved.
Chang's founding promise — still operative today, embedded in TSMC's articles of incorporation:
TSMC will never compete with its customers. No TSMC-branded chip has ever shipped.
This is not strategic positioning. It is a constitutional constraint that Morris Chang designed
to be credible across CEO transitions, economic cycles, and shareholder pressure.
Why the promise is the moat
When Apple designs the A-series chip, Apple's silicon team works alongside TSMC process engineers
— sharing design rules, performance targets, and process feedback at a level of intimacy
that only a non-competitor earns. NVIDIA gave TSMC the Blackwell GPU design — the most
complex chip in history. This trust is the root cause of the customer feedback loop
that trains TSMC's process beyond anything internal R&D could achieve.
The promise is what made the feedback loop possible. The feedback loop is what made
the yield advantage possible. The yield advantage is what made the pricing power possible.
It is turtles all the way down — and the turtle at the bottom is a constitutional promise
made by a 56-year-old in 1987.
[Acquired — Morris Chang interview]
Part 2 — Transistor Physics (The Real Technical Foundation)
Why transistors needed to be reinvented
To understand what TSMC actually does and why it's hard, you need to understand the physics
problem that forced the transistor architecture to change. This is not background — it is
the technical foundation of TSMC's current process lead.
The short-channel effect — why FinFET existed and why it's ending
A transistor is a voltage-controlled switch. The gate controls whether
current flows through the channel from source to drain. For the switch
to be "off," the gate must be able to suppress this current completely.
The problem at small scales: as you shrink the transistor, the channel length (distance
from source to drain) gets shorter. At very short channel lengths, the drain's electric
field starts penetrating the channel region and lowering the energy barrier — even when
the gate is "off." This is called drain-induced barrier lowering (DIBL).
The result: current leaks through even when the transistor is supposed to be off.
Leakage current = wasted power = heat = lower performance = battery drain.
FinFET (Fin Field Effect Transistor), introduced at 22nm by Intel and 16nm by TSMC,
attacked DIBL by standing the channel up vertically as a thin fin, letting the gate
wrap around three sides. More gate surface area per unit of silicon = better electrostatic
control = better suppression of leakage. It worked — through 16nm, 10nm, 7nm, 5nm, 4nm, 3nm.
But below ~3nm, the FinFET fin becomes too narrow to be physically stable, and
quantum tunneling effects begin: electrons don't need an energy pathway — they
probabilistically tunnel through the barrier. The three-sided gate can no longer
overcome these quantum effects. FinFET hit a physics wall.
FinFET — 3 sides of gate control
Used: 22nm → 3nm (2012–2024)
Gate wraps 3 sides. Bottom of channel is uncontrolled — drain field penetrates here at
short channel lengths, creating leakage even when "off." At sub-3nm gate lengths,
quantum tunneling makes this unmanageable.
GAA Nanosheet — 4 sides of gate control
Used: 2nm and below (N2, A16, …)
Gate completely surrounds each horizontal silicon nanosheet on all 4 sides.
No surface is exposed to the drain's electric field. DIBL is structurally eliminated.
Nanosheet width can be tuned: wider = more current (performance), narrower = lower leakage (efficiency).
TSMC N2: 10–15% faster at same power, or 25–30% less power at same speed vs. N3E.
[PatSnap]
Why nanosheet width is a performance tuning knob
Unlike FinFET where fin height was fixed by process, GAA nanosheet width is a design parameter.
Apple can ask TSMC for wider nanosheets in the CPU cores (maximizing drive current for peak
single-thread performance) and narrower nanosheets in efficiency cores (minimizing leakage for
background tasks). This per-sheet tunability gives Apple Silicon its dramatic performance/power
envelope advantage. It is not possible in FinFET.
Part 3 — The BEOL Problem (The Half the Headlines Miss)
Transistors are the front end. Wires are the back end. Wires are now the bottleneck.
Semiconductor fabrication has two distinct phases: FEOL (front-end of line)
builds the transistors. BEOL (back-end of line) builds the metal interconnect
layers — the wiring that connects transistors to each other and to the outside world.
Every chip has 10–15+ BEOL metal layers stacked above the transistors.
For decades, FEOL (transistor scaling) was the bottleneck. GAA has now addressed FEOL.
But BEOL has quietly become equally important — and for a physics reason that is
counterintuitive: as wires get thinner, their resistance goes up faster than their
cross-section shrinks.
The copper resistance catastrophe
In bulk copper, electrons scatter off atoms roughly uniformly through the metal volume.
Resistance scales predictably with length and inversely with cross-section. But at sub-10nm
wire widths, electrons scatter disproportionately off surfaces and grain boundaries
— the wire has so much surface area relative to its volume that surface scattering dominates.
Resistance per unit length explodes. This is called the size effect and
it makes copper wiring increasingly problematic below ~10nm pitch.
BEOL metal layer stack — N2 process (simplified)
M9–M12 (global routes)
Cu — thick, low resistance
Power + long signals
M5–M8 (semi-global)
Cu + Ru liners
Block-to-block routing
M2–M4 (local routes)
Ru / RuCo ← critical
Cell-level connections
M0–M1 (gate layer)
Ru — sub-10nm pitch
Direct gate contacts
TRANSISTORS (FEOL)
GAA Nanosheet — N2
Source / Drain / Gate
At the M0–M1 layers (closest to transistors), wire pitches are now below 10nm.
Copper's surface-scattering size effect makes it unusable here — TSMC switches to
ruthenium (Ru) and RuCo alloys, which have lower
resistivity than copper at sub-10nm widths due to better grain structure and
lower surface-scattering sensitivity.
[Semiconductor Engineering]
TSMC's N2 process uses ruthenium and RuCo alloys for the tightest local metal layers.
This is a major materials science shift — replacing the metal that has defined chip
wiring for 30 years. Qualifying a new interconnect material requires years of process
development: adhesion, electromigration resistance, via resistance, reliability under
thermal cycling. It is as hard as qualifying a new transistor architecture, and it
happens simultaneously. This dual-track complexity (FEOL + BEOL both changing together)
is why only TSMC can maintain the development cadence it does.
Part 4 — Backside Power Delivery: A16's Defining Innovation
Why moving power to the back of the chip is harder than it sounds
Every transistor needs two things: a signal path (gate input, drain output) and a power
supply (VDD/VSS). In all chips built before A16, both share the same limited real estate
above the transistors — the BEOL metal stack. This creates two problems:
IR drop. Power current (I) flows through resistive metal wires (R),
causing a voltage drop V = IR. At the transistor level, this means the actual VDD
seen by a transistor can be 50–100mV lower than the supply voltage. Since transistor
switching speed is proportional to (VDD − Vth)², even a 5% voltage drop reduces
performance by ~10%. For AI chips drawing 1000W+ across billions of transistors,
IR drop is a primary performance limiter.
Routing congestion. Power rails consume precious routing tracks in M1–M4,
leaving less room for signal wires. At 2nm densities, this congestion forces
suboptimal placement of logic cells — you can't put two cells next to each other
if the power rail route between them blocks the signal path.
Frontside vs. Backside Power Delivery — schematic cross-section
TSMC's Super Power Rail connects directly to each transistor's source and drain from below,
through selective through-silicon contacts. This is more complex than Intel's PowerVia
(which uses nano-TSVs) but achieves lower resistance at the transistor connection point.
Result: 8–10% speed improvement or 15–20% power reduction at same design. For an AI GPU
drawing 1kW+, 15% power reduction means hundreds of watts less heat in the package.
[TSMC A16 official]
Part 5 — CoWoS: Complete Technical Deep Dive
The chip node is not where AI supply breaks. Packaging is.
The AI chip supply constraint since 2023 has not been about N3 or N5 wafer capacity —
it has been about CoWoS (Chip-on-Wafer-on-Substrate), TSMC's advanced
packaging platform. Understanding CoWoS in detail is understanding the real technical
and economic constraint on AI hardware supply through 2027.
5.1 — Why packaging matters: the memory wall problem
The fundamental problem driving CoWoS demand: GPU compute has grown 3× faster than
GPU memory bandwidth over the last decade. An H100 GPU can perform 3,958 TFLOPS of
tensor compute but can only feed data at 3.35 TB/s from its memory — meaning the
arithmetic units sit idle waiting for operands. This is the roofline model:
for matrix-multiply-heavy AI workloads, every AI model has an arithmetic intensity
(FLOPS per byte fetched) below which bandwidth is the bottleneck, not compute.
Bandwidth bottleneck — simplified roofline
Arithmetic intensity (AI workloads) = 10–100 FLOPs / byte H100 compute ceiling: 3,958 TFLOPS ÷ 3.35 TB/s bandwidth = 1,182 FLOPs/byte → Most transformer inference is bandwidth-bound, not compute-bound
Every 1 TB/s bandwidth increase ≈ same AI throughput gain as adding ~1,200 TFLOPS Memory bandwidth is the real AI chip performance metric — not TFLOPS.
This is why the B200 is so valuable: 8 TB/s vs. H100's 3.35 TB/s = 2.4× bandwidth → 2.4× real-world AI throughput at the same arithmetic intensity
You cannot achieve >3 TB/s bandwidth with standard DRAM sitting on a PCB connected via
PCIe. The wire lengths are too long, the interface too narrow, the pin density
impossible. The only solution is to bring memory physically adjacent to the GPU —
micrometers apart instead of centimeters — and use a wide bus. That is CoWoS.
5.2 — The three CoWoS variants (S / R / L) — not all CoWoS is equal
TSMC offers three generations of CoWoS that trade off size, routing density, cost, and bandwidth.
Investors and engineers often conflate them. They are meaningfully different products.
CoWoS-S
Silicon Interposer
Structure: Full passive silicon interposer manufactured using 65nm or 28nm litho. GPU die and HBM stacks placed on top, interconnected through the Si interposer's copper routing.
Max size: ~1 reticle field (~820mm²). Hard physical limit — a single silicon interposer can't be larger than one EUV exposure field.
Routing density: ~0.4–0.8μm metal pitch. Very high. This is what makes it silicon, not organic.
HBM stacks supported: 4–6
Customers / chips: NVIDIA A100, H100, H200. Most datacenter AI chips pre-2024.
Bandwidth: 3–5 TB/s · Cost: $$$
CoWoS-R
RDL Interposer
Structure: Redistribution Layer interposer built from polymer dielectric + fine-pitch copper traces. Not silicon — closer to advanced PCB-class, but far denser than standard organic substrate.
Max size: Not reticle-limited — can be large (>2,000mm²). Fabricated by roll-to-panel process, not wafer process.
Routing density: ~2–5μm metal pitch. 3–10× lower density than CoWoS-S. The tradeoff for size.
HBM stacks supported: 2–4 (fewer, wider spacing)
Customers / chips: Some AMD, Marvell, lower-bandwidth AI chips. Suitable when bandwidth need is moderate and cost sensitivity is high.
Bandwidth: 1–3 TB/s · Cost: $$
CoWoS-L
Local Si Interconnect (LSI)
Structure: Organic substrate base (not size-limited) with embedded small silicon bridge tiles at exactly the GPU–HBM interfaces. The silicon is only where the density is needed; the rest is organic.
Max size: No practical limit — B200 package is ~5× reticle area. Multiple GPU dies can sit side-by-side.
Routing density: Silicon-level density at die interfaces (~0.4μm pitch), organic density elsewhere. Best of both worlds.
HBM stacks supported: 8–12. The only format that can support this many.
Customers / chips: NVIDIA B200, GB200, B300 — the entire Blackwell family. This is the gold standard for frontier AI.
Bandwidth: 8+ TB/s · Cost: $$$$
Why Intel's EMIB and TSMC's CoWoS-L solve the same problem differently
Intel's EMIB (Embedded Multi-die Interconnect Bridge) places small silicon tiles in the organic
substrate specifically at die-to-die interfaces — exactly the CoWoS-L concept. Intel used EMIB
for Ponte Vecchio (2022 datacenter GPU). TSMC's CoWoS-L uses the same principle but TSMC
manufactures the silicon bridges, the organic substrate, and does the final assembly all at
one site. Intel must coordinate between its own fab (bridge tiles), an external substrate vendor,
and its own assembly line — three parties vs. TSMC's one. This single-site integration is
a process yield and throughput advantage.
[SemiAnalysis — CoWoS deep dive]
5.3 — HBM: what is actually in that memory stack
HBM (High Bandwidth Memory) looks like a single chip but is a vertical stack of multiple
DRAM dies connected through the silicon using through-silicon vias (TSVs).
This is not the same as the Tao's Law LogicFolding concept (which folds within one die) —
HBM stacks separate manufactured dies on top of each other.
HBM3E Die Stack — cross-section (12 dies + base die)
DRAM #12
DRAM die — ~50μm thinned Si
DRAM #11
DRAM die — ~50μm thinned Si
· · · (12 dies total, each 2GB) · · ·
DRAM #2
DRAM die — ~50μm thinned Si
DRAM #1
DRAM die — ~50μm thinned Si
Base die
Memory controller · sense amps · I/O · PHY circuitry
microbumps (40μm pitch) → to interposer
TSV key facts:
• Diameter: ~5–8μm
• Height: ~50μm (full die thickness)
• Fill: electroplated copper
• Pitch: 40μm between TSVs
• Per HBM3E stack: ~102,400 TSVs
Die thinning process:
Raw DRAM wafer = 775μm thick.
Backgrind after TSV etch: ~50μm.
At 50μm, die is semi-transparent.
Handling requires wafer-on-carrier.
B200 HBM3E per stack:
• 12 DRAM dies (not 8 — B200 uses 12-high HBM3E)
• 24GB per stack (12 × 2GB)
• 1,024-bit interface (bus width)
• 8 stacks → 192GB total
• Manufactured by SK Hynix / Samsung / Micron
TSVs are what make HBM possible: they provide the vertical electrical highway through
50μm-thin silicon dies. The manufacturing challenge — drilling, lining, and filling
millions of 5μm holes through silicon — requires specialized etch and deposition equipment
(not the same as standard FEOL). SK Hynix leads HBM3E supply; Micron is ramping; Samsung
has faced quality issues. TSMC does the CoWoS interposer assembly but does not
make the HBM itself — that supply chain dependency is a separate risk vector.
[TechInsights HBM teardown]
5.4 — The bandwidth math: why 1024-bit bus × Gbps = game-changer
The reason CoWoS enables such disproportionate bandwidth is a combination of interface
width and proximity. With HBM on the same interposer as the GPU, you can run a
massively wide bus at moderate per-pin speed — the opposite of PCIe (narrow bus,
high per-pin speed). Wide bus = lower per-pin clock rate = lower power, lower latency.
Bandwidth calculation — NVIDIA B200
8 HBM3E stacks × 1,024 bits/stack = 8,192-bit total bus 8,192 bits × 8.0 Gbps per pin ÷ 8 bits/byte = 8.19 TB/s
vs. traditional GDDR7 on PCB (RTX 5090 for comparison)
512-bit bus × 28 Gbps/pin ÷ 8 = 1.79 TB/s Bus width ratio: 8,192 / 512 = 16× wider bus Per-pin speed: CoWoS runs at 8 Gbps vs. GDDR7's 28 Gbps CoWoS wins by going extremely wide, not extremely fast per pin
Why can CoWoS run a 16× wider bus? Because HBM sits 55μm away (wire length on interposer)
vs. GDDR7 sitting 30–80mm away (wire on PCB). Shorter wire → lower capacitance → lower
power per bit transferred → can afford 8,192 signal lines instead of 512.
HBM bandwidth roadmap — per stack
HBM2 (2016): 256 GB/s/stack — 8 dies × 128-bit? — H100: 3.35 TB/s (8 stacks H100 SXM) HBM3E (2024): 1.15 TB/s/stack — 12 dies × 1024-bit — B200: 8 TB/s (8 stacks) HBM4 (2026-27): ~1.5+ TB/s/stack — 2048-bit bus (double the interface width) HBM4 → 8 stacks × 1.5 TB/s = 12+ TB/s possible for next-gen AI chips
HBM4 moves to 2048-bit interface by narrowing die spacing to 30μm (from 40μm).
This requires even better TSMC CoWoS alignment accuracy — tolerance tightens from ±2μm to ±1μm.
The interposer manufacturing challenge scales with each HBM generation.
5.5 — Full B200 package: what TSMC actually assembles
4nm N4P · ~800mm² each · 208B transistors (Hopper had 80B). Two dies interconnected via NVLink-C2C at 900 GB/s bidirectional on the interposer — eliminates PCIe bottleneck between GPU halves.
HBM3E #1 24GB
HBM3E #2 24GB
HBM3E #3 24GB
HBM3E #4 24GB
HBM3E #5 24GB
HBM3E #6 24GB
HBM3E #7 24GB
HBM3E #8 24GB
↕ micro-bumps: ~10μm pitch (Cu pillar + solder cap) — 100,000s of connections per die
Local Silicon Interconnect Bridge Tiles (CoWoS-L)
Small silicon dies (~5mm×5mm each) embedded in organic substrate at exactly the GPU↔HBM and GPU↔GPU interface locations.
Manufactured by TSMC using 65nm lithography. Each bridge tile has ~0.4μm copper wire pitch.
Total package: ~5× reticle area (~4,100mm²). Bridge tiles cover ~15% of package area but carry 100% of the critical high-density IO.
Everything else (power, lower-bandwidth signals) routes through the organic substrate.
8–12 metal layers. Wire pitch: ~15–25μm (coarse vs. Si bridge). Provides power planes (VDD, VSS),
ground planes, and coarse signal routing. BGA (ball grid array) on underside connects to SXM5 server board.
Total package dimensions: ~93mm × 80mm. Made by ASE / Ibiden (substrate vendors) not TSMC.
The NVLink-C2C connection between the two Blackwell GPU dies (running at 900 GB/s bidirectional,
on the interposer) is what makes B200 act as a single logical GPU rather than two.
Without CoWoS-L's silicon-level routing density, this GPU-to-GPU link wouldn't have
enough bandwidth to be transparent. This is the second major function of the interposer —
not just GPU→HBM, but GPU→GPU.
5.6 — The CoWoS assembly process: why it's hard to replicate
Understanding what TSMC physically does during CoWoS assembly explains why this process
is hard to ramp and why competitors can't simply copy it.
Wafer-level bonding (not die-level). TSMC places GPU dies and HBM stacks
onto the interposer while both are still in wafer form — before dicing into individual packages.
This is called "chip-on-wafer" (CoW). The advantage: placement machines work on a flat wafer,
achieving ±0.5μm alignment accuracy across thousands of packages simultaneously. Die-level
assembly (flip-chip) typically achieves ±5–10μm. The extra precision is what allows
10μm micro-bump pitch (vs. 130μm C4 bumps on the organic substrate). The "wafer-on-substrate"
step then mounts the diced CoW units onto their organic substrates.
Thermo-compression bonding (TCB). Micro-bumps are Cu-pillar + SnAg solder cap structures.
During bonding, a heated tool presses the die onto the interposer at precisely 200–260°C and
controlled pressure for 2–5 seconds per die. The solder cap melts and re-solidifies, forming
a joint. At 10μm pitch with 100,000+ bumps per die, any thermal expansion mismatch between
the GPU die (silicon, 2.6 ppm/°C) and the interposer (also silicon, 2.6 ppm/°C, conveniently)
must be controlled to <0.1μm during the bonding window. This is why a silicon interposer
is preferred over organic (4–17 ppm/°C) for high-bump-count bonding.
Underfill dispensing. After bonding, liquid epoxy is dispensed around each
die and wicked under by capillary action, encapsulating all micro-bumps. Underfill prevents
thermal-cycling fatigue cracks at the bump joints — critical because the package goes from
ambient temperature to 80°C operating temperature thousands of times over its life.
Underfill development for 10μm pitch (narrower gap = harder capillary flow) required
years of materials R&D. TSMC co-developed specific formulations with Henkel and Namics.
Yield test at each stage. After wafer-level placement (before dicing), TSMC
does electrical probing across the full CoW wafer. Known-good dies (KGD) are identified.
This is not standard for conventional packaging — it requires custom probe cards at
wafer-scale that can contact 10μm bumps. Only TSMC has this at volume.
5.7 — Compound yield: why AI chips are expensive
Every step in the CoWoS assembly adds its own yield loss on top of the silicon node yield.
This compound yield is the real driver of AI chip pricing — not just node wafer cost.
~75%
N4P GPU die yield at node
×
~90%
65nm interposer yield (mature node)
×
~97%
HBM stack yield (KGD only)
×
~96%
CoWoS bonding assembly yield
=
~63%
Good B200 packages shipped
63% final package yield means ~37 failed/rejected B200 units for every 100 started.
Each B200 GPU die is ~$6,000–8,000 in wafer cost alone. 37 failed units × $7,000 = $259,000
in die scrap per 100 units, which must be priced into the $30,000–40,000 B200 SXM5 unit price.
Yield improvement compounds dramatically here: going from 63% → 70% package yield at TSMC's
CoWoS scale (tens of thousands of units/month) unlocks hundreds of millions in cost savings.
This is why TSMC's process engineers spend as much time on CoWoS yield as on node yield.
HBM as a separate supply chain risk
TSMC controls the CoWoS bonding yield but does not control HBM yield or supply.
SK Hynix makes ~50% of all HBM (with dominant share at HBM3E).
Samsung makes ~30% but has faced yield and quality issues.
Micron makes ~20% and is ramping fast.
If SK Hynix has a production disruption — fire (Icheon fab fire risk), flooding, or
equipment failure — TSMC can't substitute. The AI GPU supply chain has a
HBM concentration risk that sits outside TSMC's control.
This is not a TSMC investment risk directly, but it is a NVIDIA revenue risk —
and NVIDIA at 22% of TSMC revenue means it matters.
5.8 — Who else does advanced packaging — and how far behind are they?
Provider
Technology
Max HBM stacks
Routing density
Where they're used
Gap to TSMC
TSMC CoWoS-L
Si bridges in organic, wafer-level bonding, ±0.5μm placement
8–12
0.4μm (at bridge tiles)
NVIDIA B200, GB200, B300; Google TPU v5; AMD MI300X
Benchmark
TSMC CoWoS-S
Full Si interposer, wafer-level bonding
4–6
0.4–0.8μm
NVIDIA H100/H200, older AI/HPC chips
TSMC own tier
Intel EMIB
Embedded Si bridge in organic (similar to CoWoS-L concept)
4–6
~0.9μm at bridge
Intel Ponte Vecchio, Meteor Lake tile connections
~2 gen behind on max HBM count and density
Samsung FOPLP / I-Cube
Si interposer-based (I-Cube) or fan-out panel-level (FOPLP)
4
~1–2μm
Samsung own chips (Exynos); some foundry customers
~2–3 gen behind; not winning external AI chip orders
ASE Group
SiP (System-in-Package), fan-out, flip-chip; no Si interposer
0–2
>5μm
Consumer electronics, mobile chips, lower-bandwidth HPC
Not in contention for frontier AI packaging
The key insight: AMD uses TSMC CoWoS, not its own or Samsung's
AMD's Instinct MI300X — their flagship AI chip, competing directly with NVIDIA H100 —
is assembled using TSMC CoWoS. AMD designed the chiplet package (4 GCD compute dies +
3 memory cache dies + 8 HBM stacks) but TSMC does the interposer fabrication and
CoWoS assembly. This means TSMC's CoWoS capacity is the binding constraint for
both NVIDIA and AMD's AI products simultaneously. It also means TSMC earns
packaging revenue from two competing AI chip vendors — a structural advantage that
no competitor can currently replicate.
[TechInsights — MI300X package]
5.9 — CoWoS investment implications for TSMC holders
CoWoS is not just a technical capability — it is a meaningful and accelerating revenue shift
with distinct margin and pricing dynamics compared to TSMC's silicon node business.
~15–20%
Advanced packaging as % of TSMC revenue (2026E)
Up from <5% in 2021. The fastest-growing segment within TSMC's revenue mix.
3.7×
CoWoS capacity ramp 2024→2026
35K → 130K wafers/month. Larger % increase than any TSMC node in comparable timeframe.
Higher ASP
CoWoS-L revenue per wafer vs. N4 silicon
A CoWoS-L wafer serving B200 GPUs generates 30–50% more revenue than a standard N4 silicon wafer — more steps, more materials, higher price per unit.
Three reasons CoWoS is structurally good for TSMC's margins over time, not just revenue:
Higher ASP with lower capex intensity than silicon nodes.
Adding CoWoS capacity (bonding tools, underfill equipment, KGD probe stations) costs
~$200M–500M per 10,000 wafers/month of new capacity — a fraction of the $5–10B/month
required for equivalent silicon node capacity expansion. Higher revenue per dollar of
incremental capex = better returns on invested capital as CoWoS scales.
TSMC's vertical integration is the moat.
A customer who needs CoWoS-L for their AI chip cannot source it elsewhere.
OSAT (Outsourced Assembly and Test) companies like ASE can't do it.
Intel does it only for Intel. Samsung does it only weakly.
This creates pricing power in advanced packaging that is independent of
silicon node pricing — a second monopoly position, co-located with the first.
HBM4 generation will expand CoWoS-L demand further.
HBM4's 2048-bit interface (vs. 1024-bit for HBM3E) requires tighter alignment tolerances
and denser routing on the bridge tiles — capabilities only TSMC has developed.
Every HBM generation upgrade drives a refresh of CoWoS capacity and a higher ASP
per unit assembled. TSMC benefits from both the node shrink and the HBM upgrade cycle.
The key CoWoS risk for investors: concentration and process complexity
NVIDIA booking 60% of CoWoS output means NVIDIA's demand trajectory is the single largest
driver of TSMC's advanced packaging revenue. If export controls tighten further —
specifically if Blackwell chips are restricted to additional markets — the demand signal
for CoWoS-L weakens immediately. Watch US BIS export rule updates as a leading indicator.
Also watch CoWoS yield announcements: assembly yield at 96–97% is good but not bulletproof.
A systemic bonding issue (wrong underfill lot, tool calibration drift at scale) could
cause a yield excursion that hits TSMC's gross margin in the quarter it occurs.
Part 6 — Five Advantages That Compound Together
Why the lead widens every year
01
Yield flywheel — 35 years of accumulated process data
Every wafer run since 1987 has generated data: how temperature variation affects yield, which equipment quirks require compensation, how photoresist behaves differently in Taiwan humidity vs. Arizona dry air. This data has been accumulating for 35 years, encoded in TSMC's process recipes, yield models, and engineering institutional memory. When TSMC ramps a new node, it starts from the deepest knowledge base in the industry.
Current evidence: TSMC's 3nm yield: ~80–90%. Samsung's 3nm yield: reportedly 35–60%, causing Samsung to lose Qualcomm and NVIDIA orders at 3nm. TSMC's 2nm: healthy 65–75% yield in early ramp (January 2026 reports) — extremely fast for a brand-new node architecture. That fast ramp is 35 years of accumulated yield learning in action.
02
Customer co-development loop — Apple and NVIDIA are TSMC's best R&D
Apple's silicon team co-develops each new process node with TSMC. They bring design constraints (power budget, die size, performance targets) that push TSMC's process to its limits — and their feedback (this contact resistance is too high, this layer has more variation than spec) feeds directly into process improvements. Apple's A18 chip in iPhone 16 was the first production customer for N3E; Apple's feedback during that ramp made N3E better for every subsequent customer.
NVIDIA's Blackwell GPU — 208 billion transistors, the most complex chip ever manufactured — was only possible because TSMC's N4P process was mature enough to yield it at scale. Manufacturing Blackwell in turn trained TSMC on yield challenges at this die size, improving future node yield models. TSMC's most demanding customers are its most productive R&D partners — and they pay TSMC to run the R&D.
03
Capital efficiency at scale — reinvestment without distress
2026 capex: $52–56B. This is more than Intel's entire market cap in 2023. Yet TSMC's capex/EBITDA sits at ~45% — a level that would signal distress at a lesser business, but at TSMC it reflects a cash machine with pricing power so complete that it can fund the world's largest manufacturing infrastructure buildout while maintaining >50% operating margins.
The mechanism: TSMC spreads R&D cost across hundreds of customers and millions of wafers per year. Intel developing a node for its own chips amortizes R&D over only its own volume. TSMC amortizes the same R&D over Apple, NVIDIA, AMD, Broadcom, Qualcomm, and 500+ other customers simultaneously. The per-customer R&D cost is structurally lower, enabling TSMC to fund the next node sooner.
04
Equipment co-development — first access, best tuning
ASML's EUV machines are not standard products off a shelf. TSMC works with ASML during machine development to specify performance requirements, and ASML tunes production machines to TSMC's specific process flows. When TSMC receives a new EUV machine, it already has months of process development data on pre-production units. When Samsung or Intel receive the same model, they start from scratch on tuning. TSMC's installed base of EUV machines (largest in the world) also means TSMC's process engineers develop the deepest operational expertise on the equipment.
05
Organizational process discipline — "the TSMC religion"
TSMC's internal culture treats process recipe adherence as non-negotiable. Deviations are flagged immediately, root-cause analyzed, and documented. Engineer career paths reward process expertise over innovation velocity. This is not conservatism — it is the discipline that converts 50% yield into 90% yield through systematic elimination of variance sources.
This culture was set by Morris Chang and reinforced across 37 years of consistent leadership. You cannot recruit it. HSMC hired Chiang Shang-yi — a genuine TSMC process legend — and the culture didn't transfer. He was one person. TSMC's discipline is distributed across 70,000+ employees who were trained inside the system. It is the most underestimated moat in the entire value chain.
Part 7 — The Process Roadmap
What TSMC is shipping, and what's coming
2023–24
N3 / N3E
3nm · FinFET · production
Apple A17, M4, NVIDIA Blackwell
2025 →
N2
2nm · GAA Nanosheet · in production · 65–75% yield
Angstrom era · announced 2026 tech symposium · details TBD
Roadmap through 2029 confirmed
How to read TSMC roadmap announcements as a tech worker
Node names are marketing. What matters at each node:
(1) MTr/mm² — transistor density; TSMC N2 ≈ 290 MTr/mm² vs N3E ≈ 167 MTr/mm².
(2) SRAM cell size — often smaller than logic density claims; SRAM limits
practical cache sizes in CPUs. Both must improve together.
(3) Yield ramp speed — faster ramp = better process maturity.
TSMC's N2 yield (65–75% in early ramp) is faster than N3's ramp was, suggesting
the GAA transition is going well.
(4) Power delivery network resistance — directly determines whether the node
achieves its power/performance claims in real chips vs. on paper.
Part 8 — Investment Analysis: What A Long-Term Holder Needs
The financial reality — and how to read through it
66.2%
Gross Margin Q1 2026
Record high. Reflects pricing power with no viable alternative for leading-edge
$128B
2025 Revenue (USD)
+37% YoY. HPC (AI) is now 61% of revenue, growing 20% QoQ
>30%
2026 Revenue Growth Guidance
Raised from prior guidance; AI accelerator CAGR revised to 56–59%
$52–56B
2026 Capex Guidance
70–80% to advanced nodes; 20–30% to packaging + specialty
~23×
Forward P/E
Appears modest for 30%+ growth; geopolitical discount embedded
~18×
EV / EBITDA
Better metric for capex-intensive business than P/E during investment cycle peak
Customer concentration — NVIDIA just overtook Apple
For the first time in TSMC's history, NVIDIA overtook Apple as its largest customer in 2025.
This is a structural shift — not a quarterly blip.
NVIDIA
22% →
22%
Apple
18%
18%
Broadcom
↑ fast
~12%
AMD
~7%
Qualcomm
~5%
Others 500+
~36%
Source: exploresemis.substack.com, TSMC 2025 annual report estimates.
Broadcom expected to challenge Apple for #2 position in 2026 on AI chip demand.
Customer concentration risk — the two-sided sword
NVIDIA at 22% of revenue is a strength (deep integration, premium pricing, locked-in orders
years ahead) and a risk (if NVIDIA's AI chip demand misses — due to export controls,
competition, or hyperscaler capex cuts — TSMC's top line feels it immediately).
Broadcom rising fast mitigates this by creating a second AI customer anchor.
Apple declining from 22% to 18% reflects slowing smartphone upgrade cycles relative to
the AI capex boom — not a loss of share.
The capex cycle and FCF — the most important thing long-term holders misread
TSMC's free cash flow (FCF) has been declining despite record profits. This confuses
investors who look at FCF yield and see a mediocre business. It is the opposite of that.
TSMC revenue vs. capex vs. FCF (illustrative; normalized to show cycle shape)
$57B
$30B
$17B
2021
$76B
$36B
$24B
2022
$70B
$32B
$16B
2023
$94B
$40B
$24B
2024
$128B
$47B
$22B
2025
>$166B
$54B
$20B?
2026E
RevenueCapexFCF
FCF is low not because the business is deteriorating — it's because capex is peaking as
TSMC front-loads Arizona + Japan + N2 + A16 capacity simultaneously. This capex will generate
revenue from 2027–2033. The correct way to value TSMC during this phase is
normalized through-cycle FCF, not spot FCF.
Valuation — what multiple is fair, and what's in the price
Metric
TSMC Current
Interpretation
Signal
Forward P/E
~23×
Looks cheap for 30%+ growth; geopolitical discount of ~5–8× P/E baked in vs. comparable US business
Reasonable
EV/EBITDA
~18×
Better lens for capex cycle. Expands when capex moderates and FCF surges 2028+
Attractive
EV/FCF
~57×
Looks expensive but misleading — FCF is depressed by peak capex. Normalize for cycle and EV/FCF is ~25–30×
Don't use raw
P/S
~14×
High but justified by 66% gross margins and 30%+ growth; semiconductor peers at lower margins trade lower
Monitor
Dividend yield
~1.2–1.5%
Dividend raised 28% in early 2026. Low yield because management is reinvesting; will grow as capex cycle peaks and FCF surges
Not the thesis
The valuation insight every long-term holder needs
TSMC trades at a ~25–30% discount to where it would trade if listed in the US as a
pure-play foundry without Taiwan geopolitical risk. This "Taiwan discount" has compressed
and expanded with geopolitical news flow, but has persisted for years.
As a long-term holder, you are being paid in expected return for accepting this
geopolitical risk — which is either an opportunity (if the risk doesn't materialize) or
a trap (if it does). The discount will not close until the geopolitical situation
structurally changes. Don't hold expecting multiple expansion from risk-discount compression
alone; hold for earnings growth, and treat any multiple expansion as a bonus.
The long-term thesis — what you must believe to hold for 10 years
Not a list of positives — a list of required beliefs. If you can't subscribe to all of these,
you should size the position accordingly:
AI compute demand is structural, not a bubble. Hyperscalers (Microsoft, Google, Meta, Amazon) are committing multi-year capex to AI infrastructure. TSMC's AI accelerator revenue CAGR of 56–59% requires this to sustain for several more years. If AI capex pulls back materially (due to ROI shortfall or demand miss), TSMC's growth decelerates sharply.
TSMC maintains process leadership through A16 and beyond. Intel's 18A is the closest technical threat. If Intel achieves competitive yield at 18A with a major anchor customer, NVIDIA or Apple starts dual-sourcing, and TSMC's pricing power erodes. This is real risk — not certain, but it needs a view.
No kinetic military conflict in Taiwan through your holding period. At 5–7% probability over any given year, over a 10-year hold the cumulative probability is ~40–50% using simple compounding. Over a 5-year hold it's ~25%. Every long-term holder needs an explicit position on this.
Overseas fab expansion doesn't fatally compress margins. Arizona chips cost 20–30% more to produce. If Arizona scales to 30% of leading-edge capacity while Taiwan margins stay flat, blended gross margins compress to ~55–58%. That's still excellent, but EPS growth decelerates. Watch Q-by-Q margin trends as Arizona ramps.
No disruptive alternative path to chips emerges. LogicFolding / Tao's Law (Lesson 2) is the most interesting alternative vector. If an architectural approach achieves equivalent AI performance without leading-edge nodes at scale, it changes demand dynamics. This is a 2030+ risk, not 2026.
Part 9 — The Geopolitical Risk (The One That Actually Matters)
The Silicon Shield — and why it's more complicated than most investors treat it
The "Silicon Shield" theory: Taiwan's indispensability to global chip supply creates deterrence
against Chinese military action. The logic is real. It is also incomplete.
The four cracks in the shield
The "seize intact" scenario is an incentive, not only a deterrent.
China's semiconductor gap (Lesson 3) is primarily a tacit knowledge and process data problem.
Capturing TSMC's fabs intact — with their process recipes, equipment configurations, and
engineering staff — would be transformative. It would not fully solve the knowledge problem
(the knowledge is in people, not just machines), but it would give China a 10-year head
start over building from scratch. Taiwan reportedly has contingency plans to destroy critical
fab infrastructure if invasion is imminent. Whether those plans would be executed
under wartime pressure is genuinely unknowable.
[Milwaukee Independent]
The shield erodes as Arizona scales.
Paradoxically, TSMC's geographic diversification — driven by US geopolitical pressure —
weakens Taiwan's deterrence value. A Taiwan producing 60% of advanced chips is less protected
than a Taiwan producing 95%. TSMC's $165B Arizona commitment is good for supply chain
resilience but bad for the deterrence thesis.
A blockade doesn't require kinetic conflict.
Taiwan imports specialty gases (NF3, WF6), chemicals, and equipment parts that can't be
stockpiled indefinitely. A naval blockade that stops raw material imports can halt
fab production within weeks — without a single shot at the fabs themselves. This is
more politically sustainable for China and less likely to trigger immediate US military
response than an invasion. The economic damage would still be catastrophic globally.
Decision-making under nationalism is not purely rational.
The Silicon Shield assumes Beijing makes a rational, cost-benefit optimal decision.
Domestic political dynamics, nationalist pressure, and miscalculation have historically
driven military decisions in ways that pure rationality models underpredict.
Geographic diversification — the honest state
Location
Node
Status
Cost vs. TW
Leading-edge share
Taiwan (Hsinchu/Tainan)
N3, N2, A16
In production
Baseline
~90% today
Arizona Fab 1
N4 (4nm)
Production Q4 2024
+20–30%
~3–5% now
Arizona Fab 2
N3 / N2
Tools Q3 2026 · prod 2027
+20–30%
~5–7% by 2028
Arizona Fabs 3–5
N2 / A16
$165B total · 2030+
+20–30%
~30% of leading-edge by 2030
Japan Fab 1 (Kumamoto)
12nm / 16nm
Production 2024
+10–15%
Mature nodes only
Japan Fab 2 (Kumamoto)
2nm (upgraded)
Delayed to H1 2029
+15–20%
Meaningful by 2030
Germany (Dresden)
28nm / 16nm
Construction · prod 2027
+15–25%
Mature nodes · auto/industrial
The honest picture for TSMC investors
Even when the full Arizona buildout completes (~2030), ~70% of TSMC's leading-edge
capacity remains in Taiwan. "Geographic diversification" is real progress but not a
Taiwan risk solution — it's a partial hedge that costs 20–30% in margin on those wafers.
The correct frame: TSMC is incrementally becoming less exposed to Taiwan tail risk, but
remains fundamentally a Taiwan story for this decade.
Practice Project — Long-Term Holder Scenario Analysis
Input your probability estimates and position parameters. The tool models your
probability-weighted expected outcome and surfaces concentration risk.
The numbers are a starting point for your own thinking — not a right answer.
Your probability estimates — three scenarios
Scenario A — Base case: AI demand holds, TSMC maintains process lead, no conflict. Scenario B — Tension without conflict: export control tightening, customer diversification pressure, multiple compression. ~30% drawdown, recovery in 2–3 yrs. Scenario C — Taiwan disruption: blockade or kinetic conflict. Production halts. 70%+ impairment, potentially permanent.
🟢 A — Base case (compounding)
75%
🟡 B — Tension, no conflict (drawdown)
20%
🔴 C — Taiwan disruption (impairment)
5%
Sum: 100% ✓
Your position parameters
TSMC as % of total portfolio
10%
Your target annual return (overall portfolio)
15%
Holding period (years)
10y
Key metrics to track every quarter
Gross margin trajectory
Current: 66.2% Q1 2026. Watch for compression as Arizona Fab 2 ramps (2027–28). Each percentage point of gross margin = ~$1.3B in annual EBITDA at current scale.
Track: Quarterly earnings — gross margin by geography when disclosed
CoWoS capacity vs. demand
Current: ~35K wafers/month, expanding to 130K by end 2026. NVIDIA has booked ~60% of output. Resolution of the CoWoS bottleneck is a 2027 revenue unlock.
Track: Quarterly mgmt commentary on CoWoS tightness / lead times
HPC % of revenue
Was 40% in 2022, is 61% in Q1 2026. This shift is the structural AI demand story. If HPC share plateaus or declines, the AI demand thesis is weakening.
Track: TSMC quarterly revenue by platform (HPC, smartphone, auto, IoT)
N2 and A16 yield / ramp speed
N2 at 65–75% in early ramp is a positive signal. Watch for ramp to 85%+ which signals process maturity and expansion of customer base beyond early adopters.
Track: TechInsights teardowns of N2 chips; TSMC commentary on node utilization
Intel 18A progress
Intel's 18A (GAA + backside power) is the only credible technical threat to TSMC's process lead in this decade. A major anchor customer win (Microsoft custom chip) is the signal that 18A is real.
PLA military exercises frequency, US carrier group deployments, cross-strait trade flows, Taiwan defense spending trajectory. Not for short-term trading — for annual thesis review.
Track: Swift Centre probability forecasts; CSIS China Power tracker
~75%
A — Compounding base case
No conflict. AI demand sustains 25–35% revenue growth. TSMC reaches A16 and beyond as the undisputed leader. Arizona ramps without fatal margin compression. Stock compounds at 15–25% annually over the decade.
~20%
B — Tensions, no conflict
Escalating China-Taiwan tensions. Export controls tighten, some customers accelerate in-house silicon or dual-sourcing plans. Multiple compression 20–40% from peak. Business fundamentals intact, eventual recovery. Time horizon is the key variable here.
~5%
C — Taiwan disruption
Military conflict or naval blockade. Taiwan production halts. Global semiconductor supply collapses. TSMC stock: 70%+ impairment. Bloomberg estimates global GDP impact ~$10T. Arizona/Japan at non-leading-edge. This is the tail you're being paid to hold.
Primary sources
Acquired — TSMC (Remastered, 2025) — 4 hours. The definitive narrative on how TSMC became what it is. Required listening if you hold the stock.
Lesson 5: NVIDIA's real moat — why CUDA's 18-year software ecosystem matters more than GPU specs, and how to evaluate AMD, Trainium, and Ascend closing the gap
Lesson 6: The transformer architecture from first principles — why the attention mechanism determines which hardware wins, and what it means for TSMC demand
Ask me anything. Good follow-ups for a tech worker:
"Walk me through the actual process steps for GAA nanosheet formation" ·
"What does an N2 process engineer actually do day to day?" ·
"How does TSMC's yield model work — what are the inputs?" ·
For an investor:
"How should I model TSMC's margins as Arizona scales to 30% of capacity?" ·
"What would a blockade actually look like for chip supply in the first 90 days?" ·
"How do I think about TSMC vs. ASML vs. NVIDIA in portfolio construction?"