Lesson 2 on Tao's Law didn't adequately cover yield for LogicFolding. This lesson fixes that first,
then answers the deeper question: why has $50B+ in Chinese investment produced no world-class foundry?
Part 1 — The yield problem Lesson 2 skipped
In Lesson 2, heat dissipation was the headlined problem for 3D stacking. But there is
an equally serious issue that compounds it: yield mathematics.
Yield is the percentage of chips on a wafer that work correctly. At advanced
nodes, defects are inevitable — dust particles, alignment errors, material impurities. Higher
yield = more working chips per wafer = lower cost per chip. TSMC's yield discipline is a primary
source of its cost advantage.
The compounding yield problem in 3D stacking
When you stack two chips (or layers), your total yield is roughly the product of
the individual yields — because both layers must work for the final chip to work.
Yield compounding: 2D baseline vs. 2-layer 3D stack
TSMC 3nm (2D)
~90%
baseline
TSMC 3D (2 layers)
~81%
0.9 × 0.9 — still viable
SMIC 7nm DUV (2D)
~30%
already marginal
SMIC 7nm 3D (2 layers)
~9%
0.3 × 0.3 — economically brutal
* Simplified model. Actual yield depends on defect density, die size, and vertical interconnect reliability.
TSMC starts at ~90% yield, so a 2-layer stack at ~81% is workable — with careful cost accounting.
SMIC at 30% yield collapses to ~9% in a 2-layer stack. At that point, the economics are ruinous
even with state subsidies: you're scrapping 91 chips for every 9 you sell.
LogicFolding's specific yield problem
LogicFolding is intra-die — folding routing paths within a single chip rather than stacking
separate dies. So the naive "multiply the yields" formula doesn't apply exactly. But it
introduces new failure modes that replace the old ones:
Vertical interconnect failures. Huawei claims 50 million vertical
"elevators" (interconnects) between layers in a LogicFolded chip. Each elevator is a
potential failure point. A single bad connection kills the chip.
Alignment errors multiply. Each vertical layer must be aligned to the
layer beneath with sub-nanometer precision. Stacking four layers means four sequential
alignment operations — errors accumulate.
Thermal stress and delamination. Heat cycling during production
causes layers to expand at slightly different rates, creating mechanical stress at
the vertical bonding interfaces. This causes microscopic delamination (layers
separating) — a slow-kill reliability failure that may not show up in initial testing.
The investor watch question for Kirin 2026
When TechInsights tears down the Kirin 2026 chip in autumn 2026, the most important
number is not density. It's yield — and Huawei will not voluntarily
disclose this. Analysts will infer it from: (a) chip pricing vs. competitors,
(b) how quickly Huawei can ramp production volume, and (c) how tightly they allocate
chips to strategic customers vs. the open market. Low yield = high price, slow ramp,
tight allocation.
Part 2 — Why $50 billion didn't buy China a TSMC
Between 2014 and 2024, China invested roughly $50 billion through the National
IC Fund (called the "Big Fund") plus hundreds of billions more through local
government matching funds, state-owned enterprises, and forced domestic procurement.
The total is estimated at $150B+.
TSMC was founded in 1987 with $220 million. In 37 years, it became the
most important manufacturing company on Earth. China has spent 680 times as much, in a
fraction of the time, and produced nothing at the same level.
This is not a failure of ambition or capital. It is a failure that reveals what money
genuinely cannot buy in semiconductor manufacturing. There are five reasons.
01
The yield learning curve cannot be purchased
Getting from 30% yield to 90% yield at a given node takes years of iterative experimentation —
thousands of wafer runs, each revealing something new about which process parameters kill yield.
This knowledge is specific to your equipment, your chemicals, your cleanroom.
You cannot transfer it by hiring someone from TSMC. They bring intuition;
your fab's process data starts at zero.
02
TSMC's customers made TSMC
Apple co-develops each process node with TSMC engineers. NVIDIA gives TSMC continuous
feedback on how GPU chips actually perform under real AI workloads. This customer
feedback loop trains TSMC's process in ways that SMIC — serving domestic customers
at the performance frontier of smartphones, not AI — cannot replicate.
World-class customers create world-class foundries. China's domestic chip designers
are not yet at the level that would train a world-class foundry.
03
Tacit knowledge is organizational, not individual
China's strategy of recruiting TSMC engineers failed not because those engineers
lacked skill — but because TSMC's knowledge is distributed across thousands of
people and decades of process data. One engineer knows their domain. No individual
knows the system. Running a leading-edge fab requires 1,000–3,000+ engineers
who share a common process language built over years of working together.
You cannot poach that. You can only grow it.
04
Billions went into fraud
A significant fraction of China's chip investment was stolen, wasted on
zombie fabs, or siphoned through corruption. The Big Fund's own leadership
was arrested for fraud in 2022. HSMC in Wuhan raised $20B and built nothing.
Multiple projects were Ponzi schemes that collapsed before producing
a single chip. When capital allocation is politicized, capital doesn't flow
to the best engineers — it flows to the best connected.
05
The equipment and materials ecosystem is 50 years deep
TSMC's fab depends on thousands of components from suppliers who have
refined their products jointly with TSMC over decades. Specialty photoresists
from Japanese companies, precision optics from German firms, process gases tuned
to TSMC's specific etch chambers. China is rebuilding this ecosystem from scratch,
simultaneously, under export controls. It is not one hard problem — it is ten
thousand medium-hard problems that all must be solved at once.
06
The model itself was wrong
China's approach was to build IDMs — companies that both design and manufacture.
TSMC's genius was to separate design from manufacturing and focus
entirely on one. This neutrality (TSMC promises never to compete with its
customers) attracted the world's best chip designers to give TSMC their most
advanced work. China's SOE model blurred this line — state-owned manufacturers
also competed in design, creating conflicts that scared off exactly the
customers who would have trained the fab.
Case Study — HSMC: The $20 Billion Ghost Fab
Wuhan Hongxin Semiconductor (HSMC) is the perfect single example of how multiple
failure modes combine. Founded in 2017 in Wuhan with support from local government,
it promised to manufacture 7nm and 14nm chips — leapfrogging years of development
to be immediately competitive with TSMC.
The pitch: HSMC raised $20B+, was ranked Wuhan's #1 most valuable
investment project, and recruited Chiang Shang-yi — a genuine TSMC veteran and
semiconductor legend — as CEO, lending the project enormous credibility.
The reality:
Founder Li Xueyan had zero semiconductor experience. Actual paid-up capital: zero.
The $20B was raised through land-backed loans from local government — not real chip investment capital.
Chiang resigned after one year, having realized the project had no viable funding or engineering substance.
By 2020, construction halted. Workers went unpaid. Equipment was repossessed.
By 2021, all staff were dismissed. Not one commercial chip was ever produced.
The project's ASML EUV machine — purchased as a trophy asset — sat unused.
HSMC was not an anomaly. QXIC (Quanxin) in Jinan, Dehuai Semiconductor, and others
followed the same pattern: government enthusiasm → inflated projections → Ponzi-style
funding → no production → collapse. Tom's Hardware documented at least a dozen
"zombie fab" projects burning billions with nothing to show.
[Tom's Hardware]
The exception that proves the rule — YMTC and NAND flash
China has one genuine semiconductor success story at near-world-class level:
YMTC (Yangtze Memory Technologies), which reached 232-layer 3D NAND
flash memory. This is worth understanding because it reveals what China can
achieve — and why logic chips are fundamentally harder.
Why memory was achievable
NAND Flash Memory
Logic Chips (CPU/GPU)
Design complexity
Regular, repetitive cell arrays — essentially the same structure repeated billions of times
Heterogeneous: billions of unique logic gates, custom circuits, specialized blocks
Process steps
Fewer, more repetitive lithography steps — lends itself to process recipe copying
100+ unique process steps, each interdependent, with complex timing and chemistry
Performance metrics
Density and endurance — measurable, copyable targets
Clock speed, IPC, power efficiency, yield at density — multi-dimensional optimization
Customer feedback
Any data center buying storage gives feedback; less design co-development needed
Apple's A-series chip process is co-designed with TSMC — extremely high-signal
EUV dependence
Lower — 3D NAND scales by stacking layers, not shrinking 2D features
High — sub-5nm logic essentially requires EUV to be economical
YMTC invented its own architecture (Xtacking) to build memory and logic layers on separate
wafers and bond them — a genuine innovation that reduced EUV dependence. It worked.
Then the US put YMTC on the Entity List in 2022, cutting off its access to US equipment
and customers. YMTC is now building production lines with domestic Chinese tools —
a second-order experiment in whether China's equipment ecosystem has caught up.
[Tom's Hardware]
Investment lesson from YMTC
China can build world-class chips when: (a) the problem is more regular and
less heterogeneous, (b) EUV dependence is lower, (c) there's a first-principles
architectural insight (Xtacking) rather than a copy attempt. The constraint is not
Chinese engineering talent — it's the organizational, knowledge, and ecosystem
barriers that are unique to leading-edge logic. Watch CXMT (DRAM) as the next
test case — DRAM sits between NAND and logic in complexity.
The history China's chip ambitions don't advertise
1987
TSMC founded with $220M — Taiwan
Morris Chang, recruited by Taiwan's government from Texas Instruments, launches pure-play foundry model. Promises customers TSMC will never compete with them. Dutch tech giant Philips contributes technology and 27.5% stake. [Acquired episode]
1990s — "Project 909"
China's first major chip investment — fails to reach leading edge
China invested ~¥100B in a national fab program. Produced chips at 0.5μm — already a generation behind Taiwan. The IDM model (design + manufacture combined) creates conflict-of-interest that repels outside customers.
2000 — SMIC founded
China's best foundry attempt — partial success
Richard Chang (former TSMC executive) founds SMIC with global ambitions. SMIC grows to be the world's third-largest foundry. But always 1–2 generations behind TSMC. Never achieves leading-edge yield or customer trust at the highest tier.
2014 — Big Fund Phase 1 ($22B)
China declares semiconductor self-sufficiency a national priority
National IC Fund ("Big Fund") launched with ~$22B. Catalyzes hundreds of billions in matching local government investment. Sets target: 70% domestic chip self-sufficiency by 2025. (Actual 2025 self-sufficiency: ~23–25%.)
2017–2021 — Zombie fab era
$50B+ in ghost projects with zero chip production
HSMC (Wuhan, $20B), QXIC (Jinan), Dehuai (Chengdu), and a dozen others raise billions from local governments, hire a few engineers, begin construction — then collapse. Fraud, mismanagement, and engineering fantasy combine.
2022 — Big Fund corruption arrests
China's own chip fund leadership arrested for corruption
Genuine technical shock: 7nm DUV chip ships in production
Huawei's Mate 60 Pro ships with a 7nm chip made by SMIC using DUV multi-patterning. Western analysts had believed this was impossible. Low yield (~30%), state-subsidized, supply-constrained — but it shipped. The first real proof of adversity-driven progress.
2026 — Big Fund Phase 3 ($47B)
Third wave of investment — with more oversight, same structural problems
China launches another $47B fund. This time with stricter anti-corruption controls following the 2022 arrests. But the yield learning curve, tacit knowledge gap, and equipment supply chain problems have not changed in kind — only in urgency.
What money can and cannot buy in chip manufacturing
What money CAN buy
What money CANNOT buy
Buildings, cleanrooms, basic equipment
The yield optimization data from 35 years of wafer runs
Individual engineers from TSMC or Samsung
The organizational knowledge system those engineers work within
EDA licenses (where available)
The 18-year CUDA developer ecosystem that makes NVIDIA's hardware worth using
Government mandates to use domestic chips
Apple or NVIDIA as a customer giving you high-signal process feedback
A prototype EUV machine (2028–2030 estimate)
The ASML supply chain of 400,000 components refined over 30 years
Aggressive production ramp targets
The discipline to shut down a promising project when yield doesn't close
Practice Project — Failure Mode Autopsy
Below are five real China semiconductor situations. For each, identify the primary
failure mode from the five categories. Some have multiple — pick the most important one.
This builds the pattern recognition that separates real chip investment analysis from headline-reading.
Raised $20B from Wuhan local government. Founder had zero semiconductor experience; paid-up capital was zero.
Hired TSMC legend Chiang Shang-yi as CEO — he resigned after one year.
No commercial chip ever produced. All staff dismissed 2021.
Primary: Fraud / misallocation — HSMC never got far enough to hit yield or tacit knowledge barriers. The capital was raised through politically-motivated land loans, not semiconductor investment logic. The hiring of Chiang Shang-yi was a credibility-lending move, not a serious engineering effort. Every other barrier is real but secondary here: the project failed before any chip process was ever seriously attempted. This is the purest example of China's "zombie fab" failure mode.
2. SMIC at 14nm node, 2019
SMIC successfully produced 14nm chips in 2019 — a real engineering achievement.
But its 14nm yield and cost structure meant it couldn't compete on price
with TSMC's 7nm chips, which offered better performance per watt at a competitive cost.
Major fabless customers (Qualcomm, NVIDIA, Apple) didn't switch their leading designs to SMIC.
Primary: Yield curve — SMIC built the physical capability but couldn't operate it at TSMC-competitive economics. This is the yield learning curve in action: you can reach a node technologically before you can reach it economically. TSMC spent years climbing from 50% yield to 90%+ at 14nm; SMIC hit the wall of yield economics before that climb was complete. The customer loop is a secondary factor — those customers didn't bring feedback because SMIC's yield made their products uncompetitive, which in turn denied SMIC the feedback that would have improved yield. A reinforcing failure loop.
3. China recruiting TSMC engineers en masse, 2018–2022
China's chip companies aggressively recruited dozens of TSMC engineers — offering 2–3×
salary multiples. Taiwan tightened laws restricting this in 2022 after Samsung and
TSMC complained of industrial espionage. China gained individual expertise but
no Chinese foundry reached competitive leading-edge capability as a result.
Primary: Tacit knowledge — This case perfectly illustrates why tacit knowledge is organizational, not individual. The engineers who left TSMC knew their domain — but TSMC's process knowledge is distributed across thousands of people and lives in years of accumulated wafer run data. An individual engineer knows how their team manages the etch chamber. They don't know why the photoresist behaves differently on Thursday mornings when humidity changes. The system knows that. The individual doesn't. China got the humans; it didn't get the system.
4. YMTC reaching 232-layer NAND in 2022
YMTC reached a genuinely world-competitive NAND flash product. Its Xtacking architecture
(building memory and logic layers on separate wafers, then bonding) reduced EUV dependence
and enabled high density. TechInsights confirmed competitive quality.
Apple briefly evaluated YMTC chips for iPhones before US political pressure intervened.
This is the success case — and customer loop explains it — YMTC benefited from a different customer dynamic than SMIC: data center customers buying NAND don't co-develop the manufacturing process the way Apple co-develops logic processes with TSMC. The technical target (density, endurance) is more legible and copyable. But critically, YMTC succeeded by finding an architectural insight (Xtacking) that bypassed EUV dependence rather than trying to replicate TSMC's process head-on. The lesson: China can compete where the problem is (a) more regular and copyable, (b) EUV-independent, and (c) susceptible to architectural innovation rather than pure process refinement.
5. Huawei's Ascend 910B AI chip, 2023–present
Huawei's Ascend 910B is a real, shipping AI accelerator — used in Baidu, Alibaba, and
ByteDance data centers under forced import substitution. On paper specs, it approaches
NVIDIA H100. In practice, Chinese hyperscalers report training throughput at
60–70% of H100. CUDA-based models require significant re-engineering to run on
Ascend's CANN software stack.
Primary: Equipment ecosystem — but the manifestation is software — The Ascend chip's hardware is real and capable. The gap isn't purely in silicon. It's in the software ecosystem: 18 years of CUDA optimization, PyTorch/TensorFlow native CUDA support, thousands of library optimizations that make NVIDIA hardware faster in practice than on paper. This is a different kind of "ecosystem" problem — not equipment supply chain, but software ecosystem. The Ascend case teaches that in AI chips specifically, the software ecosystem IS the moat, and hardware specs alone don't capture it. This is why Lesson 4 (NVIDIA's CUDA) matters so much.
The bottom line for investors
China will not have a TSMC equivalent within any reasonable investment horizon — not because of
a lack of will, engineers, or money, but because the specific things that make TSMC irreplaceable
(yield knowledge, customer feedback loops, equipment ecosystem depth, organizational process
culture) are time-denominated assets. They compound over decades.
They cannot be acquired, only grown.
The correct investment conclusion is not "China's chip industry is hopeless." It is more nuanced:
At mature nodes (28nm+): China is already world-competitive and will dominate domestic consumption. SMIC, HuaHong, and peers are real businesses.
At advanced logic (sub-7nm): China is 5–10 years behind and the gap may be widening, not closing. Export controls are the accelerant, not the cause.
In memory (NAND, DRAM): China is closer to competitive than in logic, and YMTC/CXMT bear watching as genuine tests of China's domestic equipment ecosystem.
The Tao's Law / LogicFolding thesis is the most interesting wildcard: if it works at yield, it changes the calculus for advanced logic by routing around the node race entirely. Autumn 2026 (Kirin 2026 launch) is the first real data point.
What comes next
Lesson 4: NVIDIA's real moat — why CUDA's 18-year software ecosystem matters more than GPU transistor counts, and how to evaluate AMD, Trainium, and Ascend closing the gap
Lesson 5: The transformer architecture from first principles — why the math of attention determines which hardware characteristics win
Ask me anything. Good follow-ups from this lesson:
"What is CXMT and should I be watching China's DRAM ambitions?",
"How do I read SMIC's financials to estimate their yield at 7nm?",
"What's the actual size of China's domestic chip market vs. what they import?"
Chip War (Chapters 28–38) — Chris Miller's account of China's semiconductor ambitions from the 1990s through the 2020s is the most readable narrative version of this history.