The device-physics floor beneath the entire industry — what a transistor is, why shrinking used to be free, why it stopped being free, and why that difficulty is itself the deepest moat.
You've studied the moats from the top down — TSMC's yield learning curve, ASML's EUV monopoly, advanced packaging. This lesson goes to the bottom: the single device every chip is built from, and the physics that turned "just make it smaller" from a free lunch into the hardest manufacturing problem on Earth. Understanding this tells you why the moats exist at all — and gives you a sharp BS-detector for node-name marketing.
Core thesis: For ~30 years, shrinking a transistor automatically made it faster, denser, and lower-power (Dennard scaling) — a free lunch that funded the whole industry. Around 2005 that lunch ended: voltage stopped scaling, leakage exploded, and progress required re-inventing the transistor's shape (planar → FinFET → GAA → CFET) and printing it with EUV. The escalating physics difficulty is exactly why the field of players collapsed from ~20 to ~3 — the device physics is the foundation of the TSMC/ASML moats.
A logic chip is billions of copies of one device: the MOSFET (metal-oxide-semiconductor field-effect transistor). It has three terminals that matter — source, drain, and gate — and it works as a switch:
Modern logic uses CMOS — complementary pairs of n-type and p-type MOSFETs — arranged so that in a steady state almost no current flows; power is consumed mainly when transistors switch. Hold that idea: it's the key to what broke.
In 1974 Robert Dennard (IBM, also the inventor of DRAM) described the bargain that would define the next three decades. Shrink every dimension of a transistor by a factor k, scale the voltage down too, and:
Because power depends on the square of voltage, scaling V down each generation crushed the per-transistor power even as you added more transistors and raised frequency. This is the engine behind both Moore's Law (transistor count doubling ~every two years — really an economic observation about falling cost-per-transistor, not a law of physics) and the decades of "free" clock-speed gains.
The free lunch ran on shrinking voltage. But voltage can't fall forever. To switch the transistor on, Vdd must stay comfortably above the threshold voltage Vt; and lowering Vt to match makes the "off" transistor leak. Two leakage currents blew up as dimensions shrank:
By ~2005, Vdd had stalled around ~1 V and couldn't go lower without leakage (static power) dominating. With the V² lever gone, power density stopped falling — the power wall. The visible symptom: clock speeds plateaued at ~3–4 GHz, where they remain ~20 years later. The industry's response was to stop chasing frequency and go parallel (multicore), then specialized (GPUs, then AI accelerators) — the entire premise of this course.
The pivot that created your portfolio: When single-thread scaling died, performance had to come from parallelism and specialization instead. That is why GPUs (L6), TPUs/ASICs (L9–L10), and advanced packaging (L5) became the growth story. The end of Dennard scaling is the root cause of the AI-hardware boom.
With voltage scaling dead, the remaining problem was electrostatic control: as the channel got shorter, the flat (planar) gate — touching the channel on only one side — lost its grip, letting the drain leak current even when "off" (short-channel effects). The fix was to wrap the gate around more sides of the channel.
| Structure | Era / node | Gate wraps… | Why it was needed |
|---|---|---|---|
| Planar MOSFET | until ~22 nm | 1 side (top) | Simple, but loses channel control as it shrinks → leakage |
| FinFET | ~22 nm (Intel 2011) → 5 nm | 3 sides (a vertical "fin") | Standing the channel up as a fin lets the gate grip 3 sides → far better control, less leakage |
| GAA / nanosheet | ~3 nm / 2 nm (Samsung 2022, TSMC N2) | 4 sides (all around) | Stacked horizontal sheets fully enclosed by gate → control at sub-3 nm dimensions |
| CFET | research, ~end of decade | 4 sides, stacked n-over-p | Stack the complementary transistors vertically to keep area shrinking when 2D shrink is exhausted |
Two more frontier tricks worth knowing: backside power delivery (Intel PowerVia, TSMC's A16) routes power on the back of the wafer, freeing the front for signal wiring and improving efficiency; and high-k metal gate (Intel, 2007) replaced the leaking SiO₂ oxide with hafnium-based material to fight gate tunneling.
Critical for diligence: the node name ("5 nm", "3 nm", "2 nm") no longer corresponds to any physical dimension on the chip. No feature in a "3 nm" process is 3 nm. The names became marketing labels around the 22 nm era. What actually matters:
Use this directly: when a company touts an "N nm" chip, ignore the number and ask for density and PPA versus the specific competing node. This is exactly the kind of claim financial media repeats uncritically — and where your technical taste (the mission) pays off.
Watch first: Asianometry — transistor-scaling and FinFET/GAA explainers — clear, engineer-level history of how each transistor structure solved the leakage problem. Read: the lithography & device chapters of Chip War (in RESOURCES.md) for how the physics drove the industry's consolidation, and Semiconductor Engineering for current GAA/CFET/backside-power coverage.
Select the best answer for each.
1. What does the gate voltage of a MOSFET actually control?
2. Under Dennard scaling, why did shrinking transistors keep power density roughly constant?
3. Around 2005, Dennard scaling ended primarily because:
4. The progression planar → FinFET → GAA is fundamentally about:
5. An investor reads "our new 2 nm chip." The technically correct response is: