Cadence and Synopsys — the design-software toll booth that every chip ever made must pass through, including NVIDIA's, AMD's, and every custom ASIC.
In your "one dollar of capex" trace, two names appeared invisibly upstream of everything: ASML, which prints every leading-edge chip, and the EDA duo, on whose software every chip is designed. You've now done ASML. This lesson finishes the pair — and with it, all seven names in your THESIS.md are grounded.
Core thesis: A modern chip has tens of billions of transistors — no human can lay that out by hand. Every chip is therefore compiled from human-readable design code into a fab-ready layout by EDA software, and that software is a two-player oligopoly (Cadence + Synopsys, with Siemens EDA third). The moat is switching costs so deep they're almost absolute: certified foundry flows, decades of accumulated IP, and engineers trained on one toolchain. EDA is the purest picks-and-shovels business in the stack — it gets paid on every design regardless of who wins any socket.
Think of chip design as a compiler pipeline. An engineer writes behavior in a hardware description language; EDA tools transform it, step by step, into a physical layout the fab can print. Each stage is a distinct, expensive tool category — and Cadence and Synopsys sell across all of them.
| Stage | What happens | Representative tools |
|---|---|---|
| 1. RTL design | Engineer writes behavior in Verilog/VHDL (Register-Transfer Level) — "what the logic does," not where it sits. | (human-authored HDL) |
| 2. Logic synthesis | RTL is compiled into a gate-level netlist — actual logic gates, optimized for timing/area/power. | Synopsys Fusion Compiler · Cadence Genus |
| 3. Verification | The largest cost — simulation, formal proof, timing. Catching a bug here vs. after a $30M+ mask set is the whole game. | Synopsys VCS · Cadence Xcelium / JasperGold |
| 4. Place & route | Physical design: place billions of gates and route the wiring between them, honoring timing and the foundry's rules. | Cadence Innovus · Synopsys IC Compiler II |
| 5. Signoff | Final checks against the foundry rulebook: static timing (STA), power, DRC, LVS. Must pass exactly or the fab won't accept it. | Synopsys PrimeTime · Cadence Tempus |
| 6. Tape-out | Output the final layout file — GDSII/OASIS — and send it to the fab. This is "tape-out." | → to TSMC / Samsung / Intel |
Every accelerator you've studied — NVIDIA's B200, AMD's MI350X, Google's TPU, Broadcom's custom ASICs — went through this exact pipeline. Broadcom's whole ASIC business (L10) is, in large part, EDA expertise applied for hire.
| Player | Position | Structure |
|---|---|---|
| Synopsys | Co-leader; strongest in synthesis, signoff, and (uniquely) a huge IP business | Duopoly |
| Cadence | Co-leader; strongest in place-and-route, custom/analog, and system design | Duopoly |
| Siemens EDA (ex-Mentor) | Clear #3; strong in verification & specific niches | #3 |
The three control the overwhelming majority of EDA; Cadence and Synopsys are the two that span the entire flow at the leading edge. The structure is durable because the switching costs are extraordinary:
Connect to L17: EDA and ASML are the two structural monopolies/duopolies at the foot of the chain. Both get paid on every chip regardless of who wins downstream — but note the difference: ASML's moat is physics + supply-chain integration; EDA's is software switching costs + foundry co-certification. Different mechanism, similar durability.
AI-assisted design. Place-and-route is a brutal optimization problem; both leaders now use reinforcement learning to explore the design space automatically — Synopsys DSO.ai and Cadence Cerebrus. These deliver real productivity gains (better power/performance/area in less engineer-time), open a new monetization tier, and — crucially — deepen the moat by making the incumbent flow even more capable and harder to leave.
IP licensing. Synopsys in particular sells silicon-proven interface IP — the pre-built blocks (PCIe, USB, DDR/HBM PHY, etc.) that chip designers license rather than build. As chips integrate more standard interfaces (and HBM/PCIe generations churn fast), this is a structural growth vector. (Arm sells CPU-core IP; Synopsys sells the surrounding interface IP — complementary.) Synopsys's pending move into multiphysics simulation (the Ansys acquisition) extends the tool footprint further up the design process.
Key technical assumption: EDA switching costs and the two-player structure are durable because every advanced node ships with co-certified incumbent tool support — no third entrant or open-source flow reaches production parity at the leading edge. Falsifier — what would change your mind:
Read first: Semiconductor Engineering — EDA / Design knowledge center — high-trust, engineer-written explainers on each stage of the flow and where the tools fit. Pair with the SemiWiki EDA coverage (in RESOURCES.md) for industry-structure context.
For the business model: read the latest Synopsys and Cadence investor decks side by side — note recurring-revenue %, backlog, and how each frames AI-design + IP as the growth story.
Select the best answer for each.
1. In the chip-design pipeline, what is "tape-out"?
2. Which best describes why EDA is a "picks-and-shovels, socket-agnostic" business?
3. What makes EDA switching costs so deep that the duopoly is stable?
4. The custom-ASIC boom (Broadcom, hyperscaler silicon) is, for EDA, best described as:
5. Which event would most directly falsify the Cadence/Synopsys durability thesis?